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2024-04-15 - 21:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Apr 15, 2024 12:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3229021630,7sleep23123199cyclictest11:45:172
1299911420,25ptp4l401ktimersoftd/307:09:423
1384821350,8sleep13123099cyclictest07:40:251
564981260,99rtkit-daemon8585-21apache207:07:080
2761721140,5sleep23123199cyclictest11:35:172
31231998975,7cyclictest33-21ksoftirqd/209:00:072
31229998072,5cyclictest9-21ksoftirqd/010:30:070
31229997971,5cyclictest9-21ksoftirqd/011:35:060
31229997871,4cyclictest9-21ksoftirqd/008:20:060
31231997763,9cyclictest33-21ksoftirqd/211:20:062
31231997763,9cyclictest33-21ksoftirqd/211:20:062
31229997668,4cyclictest9-21ksoftirqd/008:25:070
31229997668,4cyclictest9-21ksoftirqd/008:25:060
31231997539,6cyclictest33-21ksoftirqd/207:55:132
308122754,58sleep20-21swapper/207:08:262
31231997437,6cyclictest33-21ksoftirqd/207:15:012
31229997467,4cyclictest9-21ksoftirqd/010:55:060
31229997466,5cyclictest9-21ksoftirqd/011:25:060
31229997466,5cyclictest9-21ksoftirqd/011:25:060
31229997464,5cyclictest9-21ksoftirqd/009:10:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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