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2024-07-27 - 07:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jul 27, 2024 00:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95421760,8sleep1501899cyclictest23:35:011
46032145123,10sleep20-21swapper/219:08:232
1299911420,4ptp4l401ktimersoftd/319:07:163
1175721160,7sleep1501899cyclictest20:30:281
5020997937,9cyclictest41-21ksoftirqd/320:20:013
45922784,18sleep10-21swapper/119:08:141
129991780,4ptp4l41-21ksoftirqd/320:40:283
5020997735,8cyclictest41-21ksoftirqd/319:50:313
277302770,6sleep127732-21fschecks_count00:30:131
5020997634,8cyclictest41-21ksoftirqd/322:00:123
5020997534,8cyclictest41-21ksoftirqd/321:15:283
158272750,8sleep0501799cyclictest20:40:190
5020997435,8cyclictest41-21ksoftirqd/300:15:133
5020997335,10cyclictest41-21ksoftirqd/321:05:273
5020997334,8cyclictest41-21ksoftirqd/323:45:113
5020997234,4cyclictest41-21ksoftirqd/319:25:003
5020997232,7cyclictest41-21ksoftirqd/321:30:013
5020997232,10cyclictest41-21ksoftirqd/319:40:283
5020997231,9cyclictest41-21ksoftirqd/322:42:093
5018997264,5cyclictest25-21ksoftirqd/121:05:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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