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2023-10-04 - 09:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Oct 04, 2023 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
383822770,7sleep00-21swapper/019:05:260
1299912520,5ptp4l401ktimersoftd/319:05:303
496421010,8sleep1540399cyclictest23:40:311
5405999280,7cyclictest41-21ksoftirqd/320:40:203
5405998374,5cyclictest41-21ksoftirqd/300:35:203
5402998312,14cyclictest17254-21cat23:00:000
5405998270,8cyclictest41-21ksoftirqd/319:55:173
5405998069,7cyclictest41-21ksoftirqd/321:20:183
50742803,19sleep20-21swapper/219:09:292
5405997865,8cyclictest41-21ksoftirqd/321:45:193
5402997713,12cyclictest8588-21acpi20:25:190
5402997713,12cyclictest21222-21sed00:15:210
114782770,8sleep0540299cyclictest22:45:380
5405997665,7cyclictest41-21ksoftirqd/322:10:193
5405997563,7cyclictest41-21ksoftirqd/322:35:223
5405997462,7cyclictest41-21ksoftirqd/300:20:193
5405997461,8cyclictest41-21ksoftirqd/323:35:153
540299748,13cyclictest17199-21sed19:35:010
485327453,10sleep10-21swapper/119:06:421
5405997361,7cyclictest41-21ksoftirqd/320:05:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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