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2024-09-08 - 18:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Sep 08, 2024 12:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1299911900,6ptp4l401ktimersoftd/307:06:203
1131821680,9sleep20-21swapper/207:05:142
1081621590,8sleep21353399cyclictest11:35:212
76821490,7sleep11353299cyclictest07:50:151
130842130109,9sleep10-21swapper/107:07:561
1690521190,8sleep31353499cyclictest08:25:033
3213421140,5sleep11353299cyclictest12:20:201
13531999479,8cyclictest9-21ksoftirqd/012:30:130
13531999479,8cyclictest9-21ksoftirqd/012:30:120
13531998672,8cyclictest9-21ksoftirqd/008:00:170
13531998371,6cyclictest9-21ksoftirqd/007:20:110
111362824,19sleep00-21swapper/007:05:050
13531998037,5cyclictest9-21ksoftirqd/012:04:590
13533997937,9cyclictest33-21ksoftirqd/212:35:002
13533997937,9cyclictest33-21ksoftirqd/212:35:002
13533997731,9cyclictest33-21ksoftirqd/207:10:172
13531997632,9cyclictest9-21ksoftirqd/008:50:170
13531997565,5cyclictest9-21ksoftirqd/009:40:120
13533997438,4cyclictest33-21ksoftirqd/210:30:012
13531997437,4cyclictest9-21ksoftirqd/011:35:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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