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2024-12-10 - 19:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Dec 10, 2024 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114142203171,21sleep20-21swapper/207:08:302
114372202168,23sleep30-21swapper/307:08:473
111992190157,23sleep00-21swapper/007:05:470
2048221760,7sleep11182499cyclictest09:50:111
112572166134,22sleep10-21swapper/107:06:321
1600721590,1sleep00-21swapper/010:45:140
1199421360,3sleep00-21swapper/010:35:230
211592950,1sleep30-21swapper/309:50:173
11825996327,9cyclictest33-21ksoftirqd/211:10:162
11825996130,6cyclictest33-21ksoftirqd/210:10:142
11825996028,4cyclictest33-21ksoftirqd/207:30:192
11825996025,5cyclictest33-21ksoftirqd/208:30:182
94942590,2sleep01182399cyclictest09:20:130
11825995930,5cyclictest33-21ksoftirqd/210:45:172
11825995927,5cyclictest33-21ksoftirqd/212:35:222
11825995927,5cyclictest33-21ksoftirqd/211:50:242
11825995927,5cyclictest33-21ksoftirqd/211:50:242
11825995924,5cyclictest33-21ksoftirqd/212:20:152
11825995924,5cyclictest33-21ksoftirqd/212:20:152
11825995924,5cyclictest33-21ksoftirqd/208:40:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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