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2022-06-29 - 14:55

x86 Intel Atom E3845 @1910 MHz, Linux 4.19.37-rt19 (Profile)

Latency plot of system in rack #d, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot4.osadl.org (updated Mon Mar 07, 2022 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1487628813,19sleep10-21swapper/107:06:031
124932790,8sleep01547199cyclictest07:45:140
151322754,59sleep30-21swapper/307:09:203
268362740,7sleep31547499cyclictest12:00:143
151732737,10sleep20-21swapper/207:09:512
222472690,4sleep233-21ksoftirqd/211:55:122
297172660,8sleep11547299cyclictest10:45:091
138662650,4sleep125-21ksoftirqd/110:25:131
15474996453,6cyclictest41-21ksoftirqd/307:15:213
15474996051,5cyclictest41-21ksoftirqd/309:40:183
294472570,2sleep30-21swapper/310:45:073
15473995612,5cyclictest33-21ksoftirqd/207:15:202
220232540,2sleep20-21swapper/209:55:162
204692540,2sleep30-21swapper/311:50:393
15473995443,5cyclictest33-21ksoftirqd/210:50:192
56598530,13rtkit-daemon0-21swapper/107:22:431
15474995343,4cyclictest41-21ksoftirqd/308:35:143
15473995338,4cyclictest33-21ksoftirqd/207:45:172
15473995324,4cyclictest33-21ksoftirqd/207:55:172
15474995242,5cyclictest41-21ksoftirqd/307:25:173
15474995242,5cyclictest41-21ksoftirqd/307:25:173
15472995238,11cyclictest801-21cron11:30:001
15472995238,11cyclictest801-21cron11:29:591
178402510,2sleep10-21swapper/111:50:091
56598490,10rtkit-daemon0-21swapper/107:37:281
301242490,2sleep230126-21cat07:25:252
301242490,2sleep230126-21cat07:25:242
15474994932,4cyclictest41-21ksoftirqd/307:55:133
15474994927,4cyclictest41-21ksoftirqd/307:45:113
15473994942,3cyclictest33-21ksoftirqd/208:35:172
15473994919,6cyclictest33-21ksoftirqd/212:00:172
264182480,2sleep20-21swapper/210:40:152
15474994831,4cyclictest41-21ksoftirqd/310:30:183
1547399484,4cyclictest121rcu_preempt12:10:112
15471994841,4cyclictest9-21ksoftirqd/008:00:170
1547499470,10cyclictest41-21ksoftirqd/310:35:183
15473994737,4cyclictest33-21ksoftirqd/209:35:192
15474994640,3cyclictest41-21ksoftirqd/308:05:183
15474994637,5cyclictest41-21ksoftirqd/309:35:183
15474994631,4cyclictest41-21ksoftirqd/308:20:403
15474994627,5cyclictest41-21ksoftirqd/308:25:123
15474994626,7cyclictest41-21ksoftirqd/309:00:113
1547399467,7cyclictest33-21ksoftirqd/208:15:012
1547399466,8cyclictest33-21ksoftirqd/208:10:552
1547399466,5cyclictest33-21ksoftirqd/208:00:072
15473994628,4cyclictest33-21ksoftirqd/211:30:292
15473994619,3cyclictest33-21ksoftirqd/209:00:192
1547399461,11cyclictest33-21ksoftirqd/208:55:172
15474994538,4cyclictest41-21ksoftirqd/307:35:173
15474994537,4cyclictest41-21ksoftirqd/311:15:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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