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2024-11-04 - 09:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot6.osadl.org (updated Sun Jun 06, 2021 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17366993420,9cyclictest13227-21cat19:35:043
17363993227,3cyclictest9-21ksoftirqd/021:55:010
1736399321,15cyclictest0-21swapper/022:30:000
17366993124,4cyclictest8262-21grep20:57:003
17363993111,17cyclictest8561-21sudo21:00:010
1736399310,16cyclictest352-21systemd-journal19:55:010
17363993016,8cyclictest21416-21timerwakeupswit20:40:180
17366992917,7cyclictest32178-21if_enp2s0.720:20:193
17366992915,8cyclictest22022-21wc21:10:173
17366992915,8cyclictest22022-21wc21:10:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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