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2024-07-27 - 08:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Jul 27, 2024 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4157597999080,7cyclictest4167186-21latency_hist19:40:000
4157597998881,5cyclictest54330-21kworker/u8:0+flush-179:000:25:010
4157600998778,6cyclictest54295-21latency_hist23:50:011
4157600998676,8cyclictest30684-21/usr/sbin/munin22:35:321
4157597998574,6cyclictest9573-21kworker/u8:3+events_unbound22:00:020
4157600998477,4cyclictest4165822-21kworker/u8:3+flush-179:019:40:271
4157597998480,3cyclictest44727-21kworker/u8:1+flush-179:023:25:240
4157597998076,3cyclictest67966-21kworker/u8:1+flush-179:000:30:240
4157597998076,3cyclictest41555-21kworker/u8:0+flush-179:023:10:250
4157597998076,3cyclictest41555-21kworker/u8:0+flush-179:023:10:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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