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2025-12-09 - 15:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Dec 09, 2025 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3157674999795,1cyclictest0-21swapper/109:47:001
3157673999686,7cyclictest3172235-21latency_hist07:55:010
3157674999472,20cyclictest3227137-21apt-get10:45:011
3157673999288,3cyclictest3251560-21kworker/u8:1+events_unbound12:25:250
3157674999182,5cyclictest3207805-21kworker/u8:1+flush-179:010:10:261
3157674998676,7cyclictest3157544-21latency_hist07:10:031
3157673998681,4cyclictest3251560-21kworker/u8:1+events_unbound12:30:250
3157673998674,4cyclictest3251560-21kworker/u8:1+events_unbound12:05:200
3157674998576,6cyclictest3160406-21kworker/u8:2+flush-179:007:20:001
3157674998549,33cyclictest3160406-21kworker/u8:2+flush-179:008:00:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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