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2023-12-02 - 06:38

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot6s.osadl.org (updated Sat Dec 02, 2023 00:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3009453997256,12cyclictest16950irq/224-800000020:15:260
300945599694,42cyclictest131rcu_preempt21:50:371
3009455996934,14cyclictest131rcu_preempt21:40:391
3009453996938,22cyclictest12-21ksoftirqd/022:45:400
3009453996938,22cyclictest12-21ksoftirqd/022:45:400
3009453996936,24cyclictest12-21ksoftirqd/022:25:290
3009453996839,22cyclictest12-21ksoftirqd/020:20:240
3009453996839,21cyclictest12-21ksoftirqd/021:45:390
300945599674,41cyclictest131rcu_preempt20:00:351
3009453996736,22cyclictest12-21ksoftirqd/000:25:330
3009453996638,20cyclictest12-21ksoftirqd/022:10:330
3009453996636,22cyclictest12-21ksoftirqd/023:30:370
3009453996635,22cyclictest12-21ksoftirqd/000:15:410
3009453996537,21cyclictest12-21ksoftirqd/023:25:320
3009453996537,20cyclictest12-21ksoftirqd/023:10:230
3009455996430,14cyclictest131rcu_preempt21:35:321
3009455996430,14cyclictest131rcu_preempt21:35:321
3009455996229,3cyclictest131rcu_preempt20:55:411
300945599594,27cyclictest131rcu_preempt22:55:331
300945599593,28cyclictest131rcu_preempt23:20:311
300945599591,27cyclictest131rcu_preempt21:25:381
300945599591,27cyclictest131rcu_preempt21:25:381
300945399591,51cyclictest0-21swapper/019:55:170
3009455995827,4cyclictest131rcu_preempt22:35:391
3009455995725,4cyclictest131rcu_preempt20:40:351
3009455995626,3cyclictest131rcu_preempt20:25:281
3009455995525,3cyclictest131rcu_preempt21:20:361
3009455995525,3cyclictest131rcu_preempt20:05:391
3009455995522,3cyclictest131rcu_preempt00:25:381
300945399544,3cyclictest131rcu_preempt22:20:270
300945399544,3cyclictest131rcu_preempt22:20:260
300945599539,4cyclictest131rcu_preempt19:25:191
300945599538,3cyclictest131rcu_preempt22:15:011
300945599528,3cyclictest131rcu_preempt20:30:321
300945599527,3cyclictest131rcu_preempt21:10:001
3009455995229,19cyclictest23-21ksoftirqd/122:50:381
3009453995228,10cyclictest12-21ksoftirqd/019:25:260
300945599519,3cyclictest131rcu_preempt20:10:281
300945599519,3cyclictest131rcu_preempt20:10:281
300945599509,3cyclictest131rcu_preempt19:15:011
300945599504,4cyclictest131rcu_preempt19:50:181
3009455995010,6cyclictest131rcu_preempt00:08:311
3009455995010,3cyclictest131rcu_preempt23:55:391
3009455995010,3cyclictest131rcu_preempt23:55:381
3009453995020,8cyclictest3014118-21sshd19:31:320
300945599498,3cyclictest131rcu_preempt20:35:381
300945599498,3cyclictest131rcu_preempt19:55:221
300945599497,3cyclictest131rcu_preempt22:25:251
300945599496,5cyclictest131rcu_preempt23:50:191
300945599495,6cyclictest131rcu_preempt00:10:181
3009455994916,3cyclictest131rcu_preempt20:45:351
3009455994911,6cyclictest131rcu_preempt19:20:001
3009453994923,3cyclictest131rcu_preempt20:10:240
3009453994923,3cyclictest131rcu_preempt20:10:240
3009453994922,10cyclictest3050968-21sed23:20:010
300945599488,3cyclictest131rcu_preempt23:10:011
300945599488,3cyclictest131rcu_preempt22:50:011
300945599487,4cyclictest131rcu_preempt23:30:241
300945599487,4cyclictest131rcu_preempt00:25:021
300945599487,4cyclictest131rcu_preempt00:25:011
300945599487,3cyclictest131rcu_preempt20:20:001
300945599485,3cyclictest131rcu_preempt22:15:231
300945599485,3cyclictest131rcu_preempt21:15:271
300945599484,4cyclictest131rcu_preempt19:40:201
300945599484,3cyclictest131rcu_preempt21:55:201
3009455994811,6cyclictest131rcu_preempt19:25:011
3009455994811,6cyclictest131rcu_preempt19:25:011
300945399487,3cyclictest131rcu_preempt22:40:340
300945399486,8cyclictest12-21ksoftirqd/021:55:000
3009453994839,5cyclictest16950irq/224-800000023:05:000
300945599477,4cyclictest131rcu_preempt23:10:271
300945599477,4cyclictest131rcu_preempt20:20:331
300945599475,4cyclictest131rcu_preempt19:45:391
300945599475,4cyclictest131rcu_preempt19:45:391
300945599475,4cyclictest131rcu_preempt19:35:021
300945599473,6cyclictest131rcu_preempt23:45:001
300945599473,5cyclictest131rcu_preempt22:40:261
300945399477,3cyclictest131rcu_preempt20:40:000
300945399475,3cyclictest131rcu_preempt00:00:000
300945399475,3cyclictest131rcu_preempt00:00:000
300945399474,3cyclictest131rcu_preempt19:25:000
300945399474,3cyclictest131rcu_preempt19:25:000
300945399473,14cyclictest3039078-21sendmail-msp22:00:000
3009453994730,9cyclictest3051446-21pluginstate23:20:300
300945399471,4cyclictest131rcu_preempt19:10:360
300945599466,3cyclictest131rcu_preempt22:20:261
300945599466,3cyclictest131rcu_preempt22:20:261
300945599466,3cyclictest131rcu_preempt21:10:181
300945599465,3cyclictest131rcu_preempt23:25:231
300945599465,3cyclictest131rcu_preempt21:30:331
300945599465,3cyclictest131rcu_preempt19:35:351
300945599464,5cyclictest131rcu_preempt20:50:221
300945599464,5cyclictest131rcu_preempt20:50:221
300945599464,4cyclictest131rcu_preempt23:40:011
300945599464,4cyclictest131rcu_preempt22:30:251
300945599464,4cyclictest131rcu_preempt00:35:161
300945599464,3cyclictest131rcu_preempt21:45:051
300945399469,3cyclictest131rcu_preempt21:25:250
300945399469,3cyclictest131rcu_preempt21:25:250
300945399468,3cyclictest131rcu_preempt23:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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