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2025-07-16 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Tue Jul 15, 2025 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318340799125114,8cyclictest3196407-21apt-get07:50:121
318340799112100,9cyclictest3246008-21apt-get10:23:231
318340599110101,7cyclictest502-21rs:main0
31834079910091,6cyclictest3221904-21kworker/u8:2+events_unbound09:10:231
3183407999993,4cyclictest3186544-21kworker/u8:1+flush-179:007:20:251
3183407999789,6cyclictest3262214-21latency_hist11:15:011
3183407999689,5cyclictest3228226-21kworker/u8:1+flush-179:009:30:141
3183405999685,8cyclictest3225053-21latency_hist09:20:010
3183407999590,4cyclictest3247679-21kworker/u8:2+events_unbound10:30:341
3183407999586,6cyclictest3218719-21kworker/u8:3+flush-179:009:15:151
3183405999380,10cyclictest3272550-21apt-get11:45:100
3183407999281,9cyclictest3267751-21kworker/u8:3+events_unbound11:35:001
3183407999184,5cyclictest3233253-21kworker/u8:0+events_unbound10:55:131
3183407999184,5cyclictest3199560-21kworker/u8:2+flush-179:008:55:261
3183407999084,4cyclictest3197181-21kworker/u8:0+events_unbound08:05:241
3183407999080,8cyclictest3288180-21kworker/u8:4+flush-179:012:35:001
3183407999080,7cyclictest3242856-21kworker/u8:1+flush-179:010:25:201
3183405999079,9cyclictest3246057-21latency_hist10:25:010
3183407998982,5cyclictest3267499-21kworker/u8:2+flush-179:011:55:161
3183407998982,5cyclictest3239675-21kworker/u8:2+flush-179:010:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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