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2024-07-27 - 07:18
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #e, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Sat Jul 27, 2024 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
4157597999080,7cyclictest4167186-21latency_hist19:40:000
4157597998881,5cyclictest54330-21kworker/u8:0+flush-179:000:25:010
4157600998778,6cyclictest54295-21latency_hist23:50:011
4157600998676,8cyclictest30684-21/usr/sbin/munin22:35:321
4157597998574,6cyclictest9573-21kworker/u8:3+events_unbound22:00:020
4157600998477,4cyclictest4165822-21kworker/u8:3+flush-179:019:40:271
4157597998480,3cyclictest44727-21kworker/u8:1+flush-179:023:25:240
4157597998076,3cyclictest67966-21kworker/u8:1+flush-179:000:30:240
4157597998076,3cyclictest41555-21kworker/u8:0+flush-179:023:10:250
4157597998076,3cyclictest41555-21kworker/u8:0+flush-179:023:10:250
4157597997974,4cyclictest4489-21kworker/u8:2+flush-179:022:20:240
4157597997874,3cyclictest44727-21kworker/u8:1+flush-179:023:35:250
4157597997765,9cyclictest55878-21latency_hist23:55:010
4157600997671,3cyclictest4176952-21kworker/u8:0+events_unbound20:20:241
4157600997670,4cyclictest45004-21kworker/u8:2+flush-179:023:25:001
4157597997665,3cyclictest41555-21kworker/u8:0+events_unbound23:15:240
4157597997569,4cyclictest4489-21kworker/u8:2+events_unbound22:30:120
4157600997461,6cyclictest9573-21kworker/u8:3+events_unbound22:10:001
4157597997469,4cyclictest48937-21kworker/u8:2+flush-179:023:40:210
4157597997368,4cyclictest6338-21kworker/u8:0+events_unbound21:20:230
4157597997368,4cyclictest4154071-21kworker/u8:0+flush-179:019:50:250
4157600997265,5cyclictest4165822-21kworker/u8:3+flush-179:019:35:291
4157597997268,3cyclictest9573-21kworker/u8:3+flush-179:022:05:310
4157597997268,3cyclictest4489-21kworker/u8:2+flush-179:022:25:270
4157597997267,4cyclictest4144461-21kworker/u8:2+flush-179:019:10:210
4157600997159,7cyclictest54330-21kworker/u8:0+flush-179:023:50:181
4157597997167,3cyclictest4173555-21kworker/u8:2+events_unbound20:05:250
4157597997166,4cyclictest4489-21kworker/u8:2+events_unbound22:15:240
4157597997166,4cyclictest4489-21kworker/u8:2+events_unbound22:15:230
4157600997062,6cyclictest27278-21latency_hist22:25:001
4157597997066,3cyclictest4187061-21kworker/u8:2+events_unbound20:50:250
4157597997066,3cyclictest30482-21kworker/u8:1+flush-179:022:40:120
4157597997066,3cyclictest30482-21kworker/u8:1+flush-179:022:40:120
4157600996959,8cyclictest9776-21/usr/sbin/munin21:30:231
4157597996964,4cyclictest44727-21kworker/u8:1+flush-179:023:55:280
4157597996964,4cyclictest44727-21kworker/u8:1+flush-179:023:55:270
4157597996961,6cyclictest4186512-21latency_hist20:40:010
4157600996862,4cyclictest4489-21kworker/u8:2+events_unbound22:10:241
415759799680,66cyclictest716-21Xorg21:04:580
4157600996756,3cyclictest35198-21kworker/u8:0+flush-179:022:50:251
4157597996762,4cyclictest36783-21kworker/u8:3+flush-179:023:05:220
4157597996759,6cyclictest35220-21latency_hist22:50:000
4157600996661,4cyclictest4154071-21kworker/u8:0+flush-179:019:45:121
4157600996660,4cyclictest4173555-21kworker/u8:2+events_unbound20:00:011
4157600996660,4cyclictest4173555-21kworker/u8:2+events_unbound20:00:001
4157597996662,3cyclictest7994-21kworker/u8:1+flush-179:021:30:480
4157597996662,3cyclictest36783-21kworker/u8:3+events_unbound22:55:300
4157600996558,4cyclictest36783-21kworker/u8:3+flush-179:023:05:211
4157597996563,1cyclictest0-21swapper/021:49:580
4157597996561,3cyclictest9573-21kworker/u8:3+events_unbound21:35:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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