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2025-05-13 - 05:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue May 13, 2025 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32569102268194,59sleep10-21swapper/119:07:341
32571372243201,28sleep00-21swapper/019:09:590
33225572730,5sleep00-21swapper/021:31:010
33976552650,4sleep10-21swapper/123:10:281
34242602580,4sleep03424261-21unixbench_multi23:45:260
125899580,7rtkit-daemon1257-21rtkit-daemon23:30:131
125899560,11rtkit-daemon1257-21rtkit-daemon00:02:490
34494412500,6sleep13449444-21switchtime00:20:281
125899500,4rtkit-daemon1257-21rtkit-daemon19:59:291
125899490,4rtkit-daemon1257-21rtkit-daemon23:18:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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