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2025-03-17 - 02:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Sun Mar 16, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255103499500497,2cyclictest2660197-21turbostat10:30:001
255103499499496,2cyclictest2750257-21turbostat12:30:011
255103499499496,2cyclictest2750257-21turbostat12:30:001
255103499482480,1cyclictest2683168-21turbostat11:04:551
255103499428426,1cyclictest2634174-21turbostat09:55:001
255103499411408,2cyclictest2634174-21turbostat09:59:551
255103499333330,2cyclictest2645438-21turbostat10:14:551
255103499332311,19cyclictest2623127-21turbostat09:40:001
255103499330328,1cyclictest2577491-21turbostat08:19:561
255103499313310,2cyclictest2668407-21turbostat10:40:001
255103499270246,22cyclictest2675060-21turbostat10:50:011
25499912264190,26sleep10-21swapper/107:05:341
255103499255249,4cyclictest2575542-21turbostat08:10:001
25494222255195,45sleep00-21swapper/007:05:210
255103499246239,5cyclictest2645438-21turbostat10:10:001
255103499246237,7cyclictest2728007-21turbostat12:00:001
255103499244237,5cyclictest2591191-21turbostat08:54:551
255103499243236,5cyclictest2716566-21turbostat11:49:541
255103499240234,4cyclictest2704707-21turbostat11:30:001
255103499239233,4cyclictest2719935-21turbostat11:54:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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