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2025-08-31 - 08:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Aug 31, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70742230166,52sleep30-21swapper/319:05:533
72302206173,22sleep20-21swapper/219:07:492
71122206174,21sleep10-21swapper/119:06:231
72692203170,22sleep00-21swapper/019:08:190
739628663,15sleep10-21swapper/119:10:011
108252810,1sleep00-21swapper/022:15:010
199992600,6sleep1768899cyclictest23:40:191
137291580,1ptp4l401ktimersoftd/323:35:253
137291570,1ptp4l401ktimersoftd/323:19:033
96582500,2sleep00-21swapper/023:19:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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