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2024-04-19 - 07:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Fri Apr 19, 2024 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
152352824460,10sleep10-21swapper/119:05:281
1524162991121,15cyclictest141rcu_preempt23:28:182
163466321050,10sleep31634654-21turbostat00:25:013
156073721010,7sleep31753-21gnome-shell20:50:313
16234772970,6sleep20-21swapper/223:50:262
152395729659,9sleep30-21swapper/319:09:213
16013902950,5chrt0-21swapper/322:50:013
152416299952,7cyclictest0-21swapper/221:32:232
152376729559,29sleep00-21swapper/019:06:570
1524162999313,17cyclictest881251-21Softwar~cThread22:45:142
1524157999385,5cyclictest0-21swapper/123:50:461
16305742910,5sleep00-21swapper/000:10:290
1524162999112,17cyclictest881251-21Softwar~cThread23:44:462
152415799912,87cyclictest0-21swapper/123:22:171
152415299915,15cyclictest141rcu_preempt22:11:400
1524157999084,4cyclictest0-21swapper/123:19:181
1524157999083,4cyclictest0-21swapper/123:28:171
1524157999083,4cyclictest0-21swapper/121:24:541
1524157999082,5cyclictest0-21swapper/120:41:091
1524157999082,5cyclictest0-21swapper/100:17:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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