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2025-03-21 - 07:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Thu Mar 20, 2025 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38346132211186,15sleep10-21swapper/107:06:441
38345782205181,14sleep30-21swapper/307:06:213
38346652202178,15sleep20-21swapper/207:07:252
38347542192168,14sleep00-21swapper/007:08:270
3835080996562,2cyclictest4112822-21kworker/u8:3+events_unbound12:35:321
383508999647,56cyclictest4112822-21kworker/u8:3+efi_rts_wq12:35:313
3835075996460,2cyclictest3839443-21kworker/u8:4+flush-179:007:20:320
3835089996360,2cyclictest3974771-21kworker/u8:2+events_unbound10:10:033
3835080996358,4cyclictest3961865-21kworker/u8:3+flush-179:011:10:291
3835075996256,4cyclictest3912819-21kworker/u8:1+events_unbound09:30:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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