You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-07-01 - 00:07

x86 Intel Xeon E3-1220 @3100 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Thu Jun 30, 2022 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2169699410405,4cyclictest32052-31munin-html10:05:322
2168499387382,4cyclictest32316-31munin-html10:05:320
2169099284280,3cyclictest32232-31munin-html10:05:321
2170299267262,4cyclictest32076-31munin-html10:05:323
311892940,0sleep30-21swapper/309:10:163
196932600,0sleep30-21swapper/309:45:163
2116125038,7sleep10-21swapper/107:06:081
2142524937,7sleep30-21swapper/307:08:433
2138024937,7sleep20-21swapper/207:08:102
2133724936,7sleep00-21swapper/007:07:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional