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2025-07-15 - 11:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Mon Jul 14, 2025 12:44:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28700862223195,18sleep30-21swapper/307:06:253
28700782203182,12sleep00-21swapper/007:06:190
28703022199154,35sleep10-21swapper/107:09:011
28703282198168,20sleep20-21swapper/207:09:222
287058099621,60cyclictest3156294-21snmp_ryswitch2.11:45:012
29082892610,2chrt2908222-21chrome07:45:023
2870587996156,4cyclictest40658-21ThreadPoolForeg08:45:003
31004982600,1chrt3100494-21apache_volume10:50:151
2870578995853,3cyclictest3114757-21/usr/share/muni11:05:031
2870587995753,3cyclictest3155553-21kworker/u8:4+flush-179:012:05:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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