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2024-10-10 - 21:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Thu Oct 10, 2024 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9595482216189,18sleep30-21swapper/307:06:173
9595482216189,18sleep30-21swapper/307:06:173
9596992210181,19sleep10-21swapper/107:08:041
9596992210181,19sleep10-21swapper/107:08:041
9596802210182,19sleep20-21swapper/207:07:482
9596802210182,19sleep20-21swapper/207:07:482
9598232181157,16sleep00-21swapper/007:09:390
9598232181157,16sleep00-21swapper/007:09:390
96720721120,1sleep00-21swapper/007:15:190
112406921070,2sleep20-21swapper/210:20:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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