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2022-06-30 - 22:41

x86 Intel Xeon E3-1220 @3100 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rackbslot1.osadl.org (updated Thu Jun 30, 2022 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2169699410405,4cyclictest32052-31munin-html10:05:322
2168499387382,4cyclictest32316-31munin-html10:05:320
2169099284280,3cyclictest32232-31munin-html10:05:321
2170299267262,4cyclictest32076-31munin-html10:05:323
311892940,0sleep30-21swapper/309:10:163
196932600,0sleep30-21swapper/309:45:163
2116125038,7sleep10-21swapper/107:06:081
2142524937,7sleep30-21swapper/307:08:433
2138024937,7sleep20-21swapper/207:08:102
2133724936,7sleep00-21swapper/007:07:510
79442470,3sleep32170299cyclictest07:40:003
89502180,0sleep10-21swapper/109:30:001
320702160,0sleep30-21swapper/311:55:113
21702991614,1cyclictest17929-21snmpd10:43:023
21696991513,1cyclictest17929-21snmpd08:36:012
21696991311,1cyclictest17929-21snmpd11:11:062
21684991312,1cyclictest17929-21snmpd10:21:270
21684991312,0cyclictest17929-21snmpd12:27:500
21684991312,0cyclictest17929-21snmpd12:27:500
21684991311,1cyclictest17929-21snmpd07:48:200
21702991210,1cyclictest4591-21/usr/sbin/munin10:15:183
21702991210,1cyclictest13729-31munin-graph08:40:413
2170299120,11cyclictest6497-31munin-html11:10:313
2170299120,11cyclictest24112-31munin-graph07:10:353
2170299120,11cyclictest22093-31munin-html08:00:293
21696991210,1cyclictest29562-21df_inode08:15:082
21696991210,1cyclictest17929-21snmpd11:15:332
21696991210,1cyclictest0-21swapper/212:05:132
2169699120,11cyclictest26261-31munin-html09:55:342
21684991210,1cyclictest17929-21snmpd10:17:190
2168499120,11cyclictest0-21swapper/012:35:280
2170299119,1cyclictest0-21swapper/307:32:523
2170299110,1cyclictest0-21swapper/310:10:373
2170299110,1cyclictest0-21swapper/308:55:123
2170299110,10cyclictest0-21swapper/309:55:263
2170299110,10cyclictest0-21swapper/309:01:013
2169699119,1cyclictest3739-21isc-worker000308:52:232
2169699119,1cyclictest0-21swapper/209:13:452
2169699119,1cyclictest0-21swapper/208:26:362
2169699110,10cyclictest0-21swapper/210:49:492
2169699110,0cyclictest4040-31munin-graph12:01:012
2169099119,1cyclictest25030-31munin-html12:35:321
2169099119,1cyclictest0-21swapper/112:01:481
2169099119,1cyclictest0-21swapper/110:20:051
2169099119,1cyclictest0-21swapper/108:40:271
2169099119,1cyclictest0-21swapper/108:30:561
2169099110,1cyclictest0-21swapper/108:05:251
2168499119,1cyclictest0-21swapper/011:50:250
2168499119,1cyclictest0-21swapper/011:24:350
2168499119,1cyclictest0-21swapper/011:00:410
21684991110,0cyclictest0-21swapper/011:15:420
2168499110,1cyclictest0-21swapper/008:25:010
2170299108,1cyclictest0-21swapper/311:49:353
2170299100,9cyclictest0-21swapper/311:31:113
2170299100,9cyclictest0-21swapper/308:53:453
2170299100,1cyclictest0-21swapper/308:06:453
2170299100,1cyclictest0-21swapper/307:27:523
2169699108,1cyclictest17929-21snmpd08:46:022
2169699108,1cyclictest0-21swapper/212:23:472
2169699108,1cyclictest0-21swapper/210:51:162
2169699100,9cyclictest0-21swapper/210:10:452
2169699100,9cyclictest0-21swapper/210:04:372
2169699100,9cyclictest0-21swapper/209:39:352
2169699100,0cyclictest0-21swapper/209:00:212
2169099108,1cyclictest17929-21snmpd11:27:391
2169099108,1cyclictest14285-31munin-html09:35:311
2169099108,1cyclictest0-21swapper/112:20:021
2169099108,1cyclictest0-21swapper/111:45:201
2169099108,1cyclictest0-21swapper/111:33:131
2169099108,1cyclictest0-21swapper/111:16:251
2169099108,1cyclictest0-21swapper/108:03:181
2169099100,9cyclictest0-21swapper/112:11:581
2169099100,9cyclictest0-21swapper/111:43:141
2169099100,9cyclictest0-21swapper/108:22:511
2169099100,2cyclictest28191-21date07:20:001
2169099100,1cyclictest0-21swapper/111:23:121
2169099100,1cyclictest0-21swapper/110:55:551
2168499109,1cyclictest17929-21snmpd09:24:090
2168499108,1cyclictest17929-21snmpd10:40:380
2168499108,1cyclictest0-21swapper/012:16:340
2168499108,1cyclictest0-21swapper/012:05:450
2168499108,1cyclictest0-21swapper/010:35:300
2168499108,1cyclictest0-21swapper/009:55:260
2168499108,1cyclictest0-21swapper/009:25:160
2168499108,1cyclictest0-21swapper/008:31:010
2168499100,0cyclictest0-21swapper/012:10:170
217029990,8cyclictest0-21swapper/309:20:523
217029990,8cyclictest0-21swapper/307:48:513
216969997,1cyclictest0-21swapper/212:35:442
216969997,1cyclictest0-21swapper/209:23:062
216969997,1cyclictest0-21swapper/208:10:372
216969990,8cyclictest0-21swapper/211:02:052
216909997,1cyclictest0-21swapper/112:27:471
216909997,1cyclictest0-21swapper/112:27:471
216909997,1cyclictest0-21swapper/111:57:361
216909997,1cyclictest0-21swapper/111:38:141
216909997,1cyclictest0-21swapper/110:25:531
216909997,1cyclictest0-21swapper/110:25:531
216909997,1cyclictest0-21swapper/110:15:431
216909997,1cyclictest0-21swapper/110:14:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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