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2019-07-17 - 02:35

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackbslot1.osadl.org (updated Fri Jan 25, 2019 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
227892650,0sleep20-21swapper/211:45:062
2171726453,7sleep20-21swapper/207:07:142
57642590,0sleep20-21swapper/209:25:062
2191725633,7sleep10-21swapper/107:09:061
2196925341,7sleep00-21swapper/007:09:440
2160425341,7sleep30-21swapper/307:06:073
269522160,0sleep00-21swapper/010:25:060
22078991514,1cyclictest12747-21snmpd09:48:463
22076991412,1cyclictest12747-21snmpd11:21:231
22078991313,0cyclictest12747-21snmpd10:12:233
22078991313,0cyclictest12747-21snmpd09:53:063
22077991312,0cyclictest12747-21snmpd12:03:272
22076991311,1cyclictest12747-21snmpd09:25:251
22075991210,1cyclictest12747-21snmpd11:38:010
22075991210,1cyclictest12747-21snmpd09:40:590
2207599120,1cyclictest12029-21ntp_states08:10:080
2207899119,1cyclictest0-21swapper/310:48:183
2207899119,1cyclictest0-21swapper/308:27:513
2207899110,1cyclictest0-21swapper/309:38:433
2207899110,1cyclictest0-21swapper/309:30:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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