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2021-10-24 - 01:48

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackbslot1.osadl.org (updated Sat Oct 23, 2021 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218272830,0sleep30-21swapper/307:55:063
147492610,0sleep00-21swapper/009:30:140
2558926048,7sleep10-21swapper/107:06:201
2552325442,7sleep30-21swapper/307:05:493
2564825341,7sleep00-21swapper/007:07:000
2553924835,7sleep20-21swapper/207:06:012
139612430,0sleep00-21swapper/012:10:180
92792310,0sleep081ktimersoftd/008:26:320
90892220,1sleep19018-31munin-graph08:25:331
220382170,1sleep322041-21missed_timers12:25:113
26120991412,1cyclictest6584-21snmpd07:42:542
26126991311,1cyclictest15509-31munin-graph09:30:393
26120991311,1cyclictest6584-21snmpd07:33:422
26113991312,0cyclictest6584-21snmpd11:45:251
26113991311,1cyclictest6584-21snmpd09:45:361
26126991212,0cyclictest6584-21snmpd09:29:483
26120991211,0cyclictest6584-21snmpd09:54:462
2611399120,1cyclictest11483-31munin-html12:05:321
2611399120,11cyclictest3485-31munin-html09:10:301
2611399120,11cyclictest11996-31munin-graph08:30:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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