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2021-01-20 - 13:22

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackbslot1.osadl.org (updated Wed Jan 20, 2021 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3174025733,7sleep10-21swapper/119:07:081
3202725633,7sleep30-21swapper/319:09:553
3184925632,7sleep00-21swapper/019:08:070
3137724935,8sleep20-21swapper/219:06:012
15222190,0sleep10-21swapper/121:05:131
32119991614,1cyclictest3657-21snmpd19:42:350
32119991513,1cyclictest3657-21snmpd20:15:510
32133991412,1cyclictest3657-21snmpd19:45:473
32123991311,1cyclictest3657-21snmpd23:52:462
3212399130,12cyclictest14986-21munin-update00:15:012
3213399120,1cyclictest10538-31munin-html19:26:053
3213399120,11cyclictest0-21swapper/322:56:193
3213399120,11cyclictest0-21swapper/322:30:293
32123991211,0cyclictest3657-21snmpd21:03:532
32123991210,1cyclictest3657-21snmpd22:41:172
32123991210,1cyclictest3657-21snmpd21:37:422
32123991210,1cyclictest3657-21snmpd21:25:462
32123991210,1cyclictest23156-31munin-graph23:31:252
32123991210,1cyclictest0-21swapper/222:50:232
3212399120,1cyclictest24283-31munin-graph19:51:202
3212399120,1cyclictest10543-31munin-html19:26:092
3212399120,11cyclictest0-21swapper/222:45:132
32122991210,1cyclictest3657-21snmpd23:25:461
32122991210,1cyclictest3657-21snmpd19:57:061
3212299120,11cyclictest0-21swapper/119:51:061
32119991212,0cyclictest3657-21snmpd23:24:340
32119991212,0cyclictest3657-21snmpd21:55:070
3213399110,1cyclictest0-21swapper/322:35:093
3213399110,1cyclictest0-21swapper/321:10:143
3213399110,0cyclictest29374-31munin-graph00:36:163
3212399119,1cyclictest0-21swapper/222:07:472
32123991110,0cyclictest635-40kipmi019:41:082
3212399110,1cyclictest0-21swapper/220:50:162
3212399110,1cyclictest0-21swapper/219:15:292
3212399110,10cyclictest0-21swapper/220:30:052
3212399110,10cyclictest0-21swapper/219:58:072
3212399110,0cyclictest0-21swapper/220:20:142
3212299119,1cyclictest3657-21snmpd19:25:411
3212299119,1cyclictest0-21swapper/123:31:301
3212299119,1cyclictest0-21swapper/123:06:001
3212299110,10cyclictest0-21swapper/123:22:461
3211999119,1cyclictest0-21swapper/020:41:010
3211999119,1cyclictest0-21swapper/000:16:140
32119991111,0cyclictest3657-21snmpd20:23:100
3211999110,1cyclictest28511-21find23:40:540
3211999110,10cyclictest0-21swapper/022:01:170
3211999110,10cyclictest0-21swapper/019:31:060
3213399108,1cyclictest0-21swapper/300:25:073
3212399109,0cyclictest3657-21snmpd19:36:322
3212399109,0cyclictest3657-21snmpd19:31:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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