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2023-01-30 - 05:17

x86 Intel Xeon E3-1220 @3100 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackbslot1.osadl.org (updated Mon Oct 10, 2022 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2352599407405,1cyclictest20703-31munin-html07:55:311
2352599406401,4cyclictest9561-31munin-html08:30:301
23525993960,1cyclictest30874-31munin-html10:00:321
2353799395393,1cyclictest16132-31munin-html09:35:323
2353799393387,5cyclictest11981-31munin-html07:40:333
2353099392390,1cyclictest16122-31munin-html09:35:322
2353099389383,5cyclictest11985-31munin-html07:40:322
2353799383378,4cyclictest6589-31munin-html08:25:333
2352599381379,1cyclictest0-21swapper/107:40:461
2353099380375,4cyclictest6581-31munin-html08:25:332
2352599380378,1cyclictest0-21swapper/108:26:101
2353799379377,1cyclictest0-21swapper/308:13:013
2351999378376,1cyclictest0-21swapper/008:07:350
2353799377375,1cyclictest0-21swapper/310:36:243
2353099376374,1cyclictest0-21swapper/208:13:012
2353099374370,3cyclictest19551-31munin-html10:35:332
2351999374372,1cyclictest0-21swapper/009:51:310
2351999368366,1cyclictest15535-31munin-html08:40:310
2351999365363,1cyclictest27518-31munin-html09:00:310
2353799364363,0cyclictest20943-31munin-html07:55:313
2353799364359,4cyclictest9575-31munin-html08:30:303
2352599364362,1cyclictest0-21swapper/108:07:351
2353099362360,1cyclictest20715-31munin-html07:55:312
2353099360355,4cyclictest9566-31munin-html08:30:312
2352599360358,1cyclictest0-21swapper/109:51:311
2353799359357,1cyclictest31087-31munin-html10:00:333
2351999357355,1cyclictest0-21swapper/009:56:280
2353099355353,1cyclictest31093-31munin-html10:00:332
2353799354353,0cyclictest0-21swapper/308:41:283
2352599354352,1cyclictest15460-31munin-html08:40:321
2353799353351,1cyclictest0-21swapper/309:16:113
2351999352350,1cyclictest0-21swapper/010:11:590
2351999352350,1cyclictest0-21swapper/008:22:020
2353099351349,1cyclictest0-21swapper/208:41:282
2352599351349,1cyclictest27397-31munin-html09:00:311
2351999351349,1cyclictest0-21swapper/008:16:180
2353099350348,1cyclictest0-21swapper/209:16:112
2352599343341,1cyclictest0-21swapper/109:56:281
2352599339337,1cyclictest0-21swapper/108:22:021
2352599338336,1cyclictest0-21swapper/110:12:001
2352599338336,1cyclictest0-21swapper/108:16:191
2351999336334,1cyclictest0-21swapper/008:10:290
2351999334331,2cyclictest18856-31munin-html09:40:310
2351999329327,1cyclictest0-21swapper/009:15:300
2352599326321,4cyclictest29974-31munin-html08:10:291
2353799322320,1cyclictest0-21swapper/308:07:353
2352599320317,2cyclictest18752-31munin-html09:40:311
2353099319317,1cyclictest0-21swapper/208:07:352
2353799318316,1cyclictest0-21swapper/309:51:313
2352599318313,4cyclictest4144-31munin-html09:15:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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