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2022-01-26 - 11:39

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #b, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackbslot1.osadl.org (updated Wed Jan 26, 2022 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242152680,2sleep3961799cyclictest19:30:323
44032630,0sleep20-21swapper/220:45:362
289132590,1sleep00-21swapper/021:28:160
935725834,7sleep30-21swapper/319:08:543
910425341,7sleep10-21swapper/119:06:281
919025232,7sleep00-21swapper/019:07:110
903524836,7sleep20-21swapper/219:05:572
304622240,1sleep030464-21missed_timers20:35:260
294592160,0sleep00-21swapper/000:10:180
42122150,0sleep10-21swapper/122:35:071
9611991412,1cyclictest23066-21snmpd20:03:562
9603991414,0cyclictest23066-21snmpd22:49:061
9617991312,1cyclictest23066-21snmpd19:25:443
9611991312,1cyclictest23066-21snmpd23:01:222
9603991311,1cyclictest23066-21snmpd23:03:311
9617991210,1cyclictest23066-21snmpd21:20:263
9617991210,1cyclictest23066-21snmpd19:45:283
9617991210,1cyclictest12595-31munin-html00:35:363
9611991210,1cyclictest5999-31munin-html23:30:332
961199120,11cyclictest0-21swapper/219:40:092
9603991210,1cyclictest23066-21snmpd00:20:091
9603991210,1cyclictest0-21swapper/120:50:291
961799119,1cyclictest23066-21snmpd20:25:143
961799110,10cyclictest7394-31munin-graph20:50:423
961799110,10cyclictest0-21swapper/322:10:193
961799110,10cyclictest0-21swapper/321:35:253
961799110,10cyclictest0-21swapper/319:36:163
961799110,10cyclictest0-21swapper/300:04:573
961199110,1cyclictest0-21swapper/220:25:412
961199110,10cyclictest0-21swapper/219:35:372
960399119,1cyclictest13956-21kworker/1:321:10:301
960399110,1cyclictest0-21swapper/123:25:381
960399110,10cyclictest24195-21strings22:15:051
960399110,10cyclictest0-21swapper/119:15:131
960399110,10cyclictest0-21swapper/119:15:131
959899119,1cyclictest0-21swapper/022:40:050
959899119,1cyclictest0-21swapper/021:46:470
959899119,1cyclictest0-21swapper/019:10:200
959899110,1cyclictest0-21swapper/000:37:280
959899110,10cyclictest0-21swapper/023:40:480
959899110,10cyclictest0-21swapper/022:20:220
961799109,1cyclictest0-21swapper/320:13:433
961799108,1cyclictest0-21swapper/323:45:243
961799108,1cyclictest0-21swapper/322:55:403
961799108,1cyclictest0-21swapper/322:21:173
961799108,1cyclictest0-21swapper/320:20:113
9617991010,0cyclictest12987-21awk22:50:053
961799100,9cyclictest0-21swapper/322:33:133
961799100,9cyclictest0-21swapper/319:19:193
961799100,9cyclictest0-21swapper/319:19:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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