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2024-05-30 - 01:23

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Wed May 29, 2024 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
343885822490,23sleep126-21ksoftirqd/107:05:181
3438699211187,14sleep20-21swapper/207:05:172
3439902210557,14sleep00-21swapper/007:09:410
34511222980,6sleep3411rcuc/307:40:023
344008999972,7cyclictest0-21swapper/207:19:192
162399960,5rtkit-daemon0-21swapper/009:03:371
162399960,5rtkit-daemon0-21swapper/009:03:371
344008999952,89cyclictest0-21swapper/207:58:522
344008999952,89cyclictest0-21swapper/207:48:592
344008999942,8cyclictest0-21swapper/207:22:372
344008999942,8cyclictest0-21swapper/207:22:362
344008999942,89cyclictest0-21swapper/207:37:132
162399940,5rtkit-daemon0-21swapper/008:48:000
3440090999380,8cyclictest3457043-21hddtemp_smartct07:55:223
344009099932,7cyclictest0-21swapper/307:30:203
344008999932,87cyclictest0-21swapper/210:36:002
344008999932,87cyclictest0-21swapper/209:48:192
344008999932,87cyclictest0-21swapper/209:16:472
344008999932,87cyclictest0-21swapper/209:07:342
344008999932,7cyclictest0-21swapper/207:32:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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