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2024-07-27 - 03:38

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Fri Jul 26, 2024 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260941199507500,4cyclictest2667309-21turbostat09:50:003
260941199507497,7cyclictest2654677-21turbostat09:15:003
260940799507498,6cyclictest2700029-21turbostat11:24:552
260940799483456,24cyclictest2642088-21turbostat08:44:552
260940799475448,24cyclictest2685386-21turbostat10:44:562
260940799475448,24cyclictest2685386-21turbostat10:44:552
260941199474453,17cyclictest2642088-21turbostat08:40:003
260941199474449,22cyclictest2633185-21turbostat08:19:553
260941199470431,20cyclictest2625942-21turbostat07:59:553
260941199466457,5cyclictest2724421-21turbostat12:34:563
260941199464457,4cyclictest2624123-21turbostat07:54:553
260941199464455,6cyclictest2681694-21turbostat10:30:003
260941199463456,4cyclictest2688944-21turbostat10:54:553
260941199460453,4cyclictest2720952-21turbostat12:24:553
260941199460451,6cyclictest2618726-21turbostat07:39:553
260941199460451,6cyclictest2618726-21turbostat07:39:553
260941199460436,21cyclictest2620562-21turbostat07:44:553
260941199459452,4cyclictest2706992-21turbostat11:44:543
260941199459452,4cyclictest2705254-21turbostat11:39:563
260941199459452,4cyclictest2705254-21turbostat11:39:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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