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2025-07-12 - 10:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Fri Jul 11, 2025 12:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25738352229200,19sleep10-21swapper/107:08:101
25737962213185,18sleep00-21swapper/007:07:390
25738222205176,19sleep30-21swapper/307:07:583
25737562205182,13sleep20-21swapper/207:07:092
28490252640,1chrt2849020-21/usr/share/muni11:35:022
2574178996310,52cyclictest2683774-21kworker/u8:0+efi_rts_wq09:00:022
257417899620,2cyclictest2673975-21/usr/share/muni08:45:022
257417599624,57cyclictest2683774-21kworker/u8:0+efi_rts_wq09:00:030
2574178996138,2cyclictest2735886-21chrome09:45:022
2574176995956,2cyclictest2714091-21kworker/u8:2+events_unbound11:15:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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