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2025-09-18 - 01:24

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00018.09. 01:10
r0s0sx86_​644 x 23,40054,39218.09. 01:10
r0s1x86_​644 x 22,30055,99218.09. 01:11
r0s1sx86_​644 x 23,30052,79218.09. 01:11
r0s2x86_​644 x 23,50055,86418.09. 01:11
r0s2sx86_​6410 x 13,70073,99018.09. 01:12
r0s3x86_​648 x 23,600115,20018.09. 01:13
r0s3sx86_​644 x 23,60067,20018.09. 01:15
r0s4x86_​648 x 23,600115,20018.09. 01:16
r0s4sx86_​648 x 23,600115,20018.09. 01:16
r0s5x86_​648 x 23,500115,20018.09. 01:18
r0s5sx86_​648 x 23,600115,20018.09. 01:18
r0s6x86_​648 x 23,600115,20028.02. 13:18
r0s6sx86_​6410 x 23,700147,98018.09. 01:20
r0s7x86_​648 x 23,600115,20018.09. 01:21
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20018.09. 01:22
r0s8sx86_​646 x 23,47083,37618.09. 01:23
r1s0x86_​644 x 13,10024,80018.09. 01:24
r1s1x86_​642 x 22,60021,69618.09. 01:24
r1s2x86_​644 x 12,30028,00017.09. 13:24
r1s2sx86_​644 x 12,30028,00017.09. 13:24
r1s3x86_​644 x 12,80022,42417.09. 13:25
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004817.09. 13:26
r1s4sarm​v7l2 x 14004817.09. 13:26
r1s5aarch​644 x 11,20079617.09. 13:27
r1s6x86_​642 x 22,13017,06417.09. 13:27
r1s6sx86_​642 x 21,66713,33217.09. 13:28
r1s7arm​v6l1 x 11,66753017.09. 13:29
r1s8i6861 x 21,6006,39817.09. 13:29
r1s8sx86_​644 x 11,90015,19617.09. 13:30
r2s0x86_​644 x 13,10024,80017.09. 13:30
r2s1arm​v5tejl1 x 120019917.09. 13:31
r2s2arm​v7l1 x 172049917.09. 13:35
r2s3arm​v7l0 x 1 x 162462417.09. 13:35
r2s3sarm​v7l0 x 2 x 16001,20017.09. 13:36
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966617.09. 13:37
r2s5sarm​v7l4 x 11,20015217.09. 13:37
r2s6i6861 x 11,5002,99917.09. 13:38
r2s6saarch​644 x 11,3506417.09. 13:39
r2s7aarch​644 x 12,40043217.09. 13:39
r2s7saarch​644 x 11,50043217.09. 13:40
r2s8ppc1 x 14006617.09. 13:43
r3s0i6864 x 23,50055,99217.09. 13:44
r3s1i6864 x 12,40019,12717.09. 13:45
r3s2riscv641 x 11,00028417.09. 13:45
r3s2sriscv644 x 1028417.09. 13:47
r3s3x86_​646 x 23,33379,99217.09. 13:47
r3s3sx86_​644 x 13,40011,98017.09. 13:48
r3s4aarch​646 x 11,3009617.09. 13:49
r3s5i5861 x 113326517.09. 13:50
r3s5sppc2 x 11,20040017.09. 13:52
r3s6x86_​641 x 21,6606,66617.09. 13:52
r3s6sx86_​642 x 22,66721,33217.09. 13:53
r3s7i6861 x 15331,06617.09. 13:54
r3s8i6864 x 13,20027,36917.09. 13:55
r4s0x86_​642 x 22,30018,40017.09. 13:56
r4s1arm​v7l4 x 11,50079217.09. 13:56
r4s1sarm​v7l4 x 11,50093617.09. 13:57
r4s2arm​v7l1 x 180079617.09. 13:58
r4s2sarm​v7l1 x 180053017.09. 13:59
r4s3i5861 x 150099617.09. 14:01
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049817.09. 14:02
r4s5arm​v7l1 x 1500017.09. 14:06
r4s5saarch​644 x 11,60020017.09. 14:06
r4s6x86_​644 x 23,40054,25617.09. 14:07
r4s6sarm​v7l0 x 1 x 11,0006617.09. 14:08
r4s7i6864 x 11,83314,66417.09. 14:09
r4s7sx86_​642 x 11,8337,33217.09. 14:10
r4s8arm​v7l1 x 140039817.09. 14:10
r4s8sarm​v7l1 x 140039817.09. 14:11
r5s0x86_​642 x 22,20017,58217.09. 14:11
r5s1x86_​648 x 13,33353,45617.09. 14:12
r5s2x86_​644 x 12,70021,69917.09. 14:12
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87217.09. 14:13
r5s3sx86_​644 x 11,60012,74817.09. 14:14
r5s4x86_​642 x 22,53020,26417.09. 14:15
r5s4sx86_​644 x 11,60012,74817.09. 14:15
r5s5arm​v7l1 x 160059717.09. 14:17
r5s5sarm​v7l1 x 160060017.09. 14:18
r5s6ppc1 x 153313317.09. 14:22
r5s7arm​v7l1 x 15286417.09. 14:22
r5s7sarm​v7l1 x 15286417.09. 14:24
r5s8x86_​644 x 12,00015,97217.09. 14:25
r6s0x86_​642 x 10 x 21,700136,18017.09. 14:26
r6s1x86_​642 x 12,0007,97817.09. 14:26
r6s2x86_​642 x 11,6679,57817.09. 14:27
r6s3x86_​644 x 22,20035,12017.09. 14:27
r6s4x86_​642 x 11,1004,37617.09. 14:28
r6s5i6861 x 11,5002,99217.09. 14:29
r6s6i6861 x 11,6003,19217.09. 14:30
r6s7i6862 x 12,3009,17617.09. 14:30
r6s8x86_​642 x 22,30018,35617.09. 14:31
r7s0x86_​642 x 22,30018,40017.09. 14:32
r7s1x86_​644 x 11,60012,83917.09. 14:32
r7s2aarch​642 x 11,7009617.09. 14:32
r7s2sriscv644 x 1028417.09. 14:34
r7s3arm​v6l1 x 1700517.09. 14:36
r7s3sarm​v7l4 x 11,40035617.09. 14:38
r7s4arm​v7l1 x 153634817.09. 14:39
r7s4sarm​v7l4 x 11,5001,08017.09. 14:40
r7s5i6861 x 11,3002,59317.09. 14:40
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76717.09. 14:41
r7s7sx86_​642 x 22,30018,39617.09. 14:41
r7s8arm​v7l1 x 11,00099517.09. 14:42
r7s8sarm​v7l1 x 11,00079617.09. 14:43
r8s0x86_​642 x 22,30018,40017.09. 14:44
r8s1i5861 x 135070117.09. 14:44
r8s3x86_​644 x 12,66721,28017.09. 14:46
r8s4x86_​644 x 21,60028,80017.09. 14:46
r8s4sx86_​644 x 21,60028,80017.09. 14:47
r8s5i6864 x 23,40054,40017.09. 14:48
r8s6arm​v7l1 x 150049817.09. 14:48
r8s6sx86_​644 x 13,30026,41617.09. 14:48
r8s7x86_​644 x 13,20025,49617.09. 14:49
r8s7sx86_​642 x 13,00011,98017.09. 14:50
r8s8x86_​642 x 11,3005,14417.09. 14:50
r9s0x86_​644 x 23,60057,60017.09. 14:51
r9s1x86_​642 x 12,0003,99217.09. 14:52
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74817.09. 14:53
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74817.09. 14:53
r9s3sx86_​644 x 13,00024,00017.09. 14:54
r9s4i6861 x 21,0003,99017.09. 14:55
r9s4sx86_​642 x 11,3335,34717.09. 14:56
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19817.09. 14:56
r9s6x86_​642 x 23,00023,94417.09. 14:57
r9s7arm​v7l2 x 11,000017.09. 14:58
r9s8sarm​v7l1 x 180079617.09. 14:58
ras0x86_​642 x 22,30018,41817.09. 14:59
ras1i6861 x 11,4002,79917.09. 15:00
ras2x86_​642 x 11,0674,26617.09. 15:00
ras2sx86_​644 x 11,90015,05217.09. 15:00
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084017.09. 15:01
ras4aarch​648 x 12,40038417.09. 15:01
ras4saarch​648 x 12,40038417.09. 15:02
ras5arm​v7l2 x 11,0002417.09. 15:03
ras5sarm​v7l2 x 11,0002417.09. 15:03
ras6aarch​648 x 12,0003,20017.09. 15:04
ras6sarm​v7l1 x 11,0001,98717.09. 15:05
ras7ppc1 x 13966517.09. 15:06
ras8x86_​644 x 11,60014,40017.09. 15:06
ras8sx86_​644 x 11,60012,74817.09. 15:07
rbs0i6862 x 22,50017,60017.09. 15:07
rbs1x86_​644 x 12,00015,97217.09. 15:08
rbs2x86_​644 x 12,00015,97217.09. 15:08
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962417.09. 15:09
rbs3sarm​v7l4 x 11,40035617.09. 15:10
rbs4x86_​644 x 11,2009,60017.09. 15:11
rbs4sx86_​644 x 11,60012,74817.09. 15:11
rbs5i6864 x 2049,41517.09. 15:12
rbs5saarch​644 x 11,6006417.09. 15:12
rbs6x86_​644 x 11,91515,32417.09. 15:13
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961217.09. 15:14
rbs7sarm​v7l4 x 19962417.09. 15:16
rbs8arm​v7l2 x 16662,65017.09. 15:17
rbs8sx86_​644 x 22,40038,70417.09. 15:18
rcs0x86_​648 x 22,40076,60817.09. 15:19
rcs1x86_​646 x 23,46783,37617.09. 15:20
rcs2x86_​642 x 12,80011,23217.09. 15:21
rcs3i6862 x 11,4005,58617.09. 15:21
rcs3sx86_​644 x 13,30026,39617.09. 15:22
rcs4x86_​642 x 11,1004,37617.09. 15:23
rcs5x86_​642 x 12,80011,19817.09. 15:24
rcs5sx86_​642 x 12,80011,19817.09. 15:26
rcs6x86_​644 x 23,50063,99217.09. 15:26
rcs7x86_​642 x 21,80014,40017.09. 15:27
rcs7sx86_​644 x 11,50011,98017.09. 15:28
rcs8x86_​6416 x 23,700217,15217.09. 15:32
rcs8sx86_​644 x 23,30052,80017.09. 15:32
rds0x86_​644 x 21,80031,99217.09. 15:33
rds1x86_​644 x 11,60012,74817.09. 15:34
rds2x86_​644 x 11,60012,74817.09. 15:34
rds3x86_​644 x 11,60012,74817.09. 15:35
rds4x86_​644 x 11,60012,74817.09. 15:35
rds5x86_​644 x 11,60012,74817.09. 15:36
rds6x86_​644 x 11,60012,74817.09. 15:37
rds7x86_​644 x 11,60012,74817.09. 15:37
rds8x86_​644 x 11,60012,74817.09. 15:37
res0x86_​644 x 23,40054,39217.09. 15:38
res1x86_​644 x 11,60014,40017.09. 15:39
res1sx86_​644 x 11,60014,40017.09. 15:39
res2x86_​644 x 11,60014,40017.09. 15:40
res3x86_​644 x 12,00015,97217.09. 15:40
res3saarch​640 x 1 x 11,0001,60017.09. 15:41
res4x86_​644 x 11,90015,05217.09. 15:42
res4sx86_​644 x 11,90015,05217.09. 15:42
res5x86_​642 x 22,20019,20017.09. 15:43
res5sx86_​642 x 22,20019,20017.09. 15:43
res6x86_​644 x 11,1008,75217.09. 15:44
res6saarch​644 x 101,60017.09. 15:45
res7arm​v7l0 x 1 x 11,0001217.09. 15:46
res7sarm​v7l0 x 1 x 11,0001217.09. 15:46
res8x86_​644 x 11,90015,05217.09. 15:47
res8sx86_​644 x 11,90015,05217.09. 15:47
rfs0x86_​6416 x 22,000127,96817.09. 15:48
rfs1aarch​644 x 11,50043217.09. 15:48
rfs1saarch​644 x 11,50043217.09. 15:49
rfs2x86_​644 x 13,00023,99617.09. 15:49
rfs2sx86_​642 x 13,00011,99817.09. 15:49
rfs3x86_​644 x 11,60012,74817.09. 15:50
rfs3sx86_​644 x 11,60012,74817.09. 15:50
rfs4arm​v7l1 x 180080017.09. 15:51
rfs4sarm​v7l1 x 180080017.09. 15:52
rfs5aarch​644 x 11,2006428.08. 05:47
rfs5saarch​644 x 11,2006427.08. 03:49
rfs6arm​v7l1 x 16671,33217.09. 15:54
rfs6sarm​v7l1 x 16671,33217.09. 15:54
rfs7x86_​644 x 22,60041,60017.09. 15:55
rfs7sx86_​644 x 17006,44817.09. 15:56
rfs8arm​v7l1 x 11,00012004.03. 03:47
 

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