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2024-05-09 - 07:56

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OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCores ↑MHzBogo​MIPSEffective
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r2s3sarm​v7l0 x 1 x 16001,20009.05. 02:00
r4s6sarm​v7l0 x 1 x 11,0006609.05. 02:50
r2s3arm​v7l0 x 1 x 162462409.05. 01:58
res3saarch​640 x 1 x 11,0001,60009.05. 05:45
res7arm​v7l0 x 1 x 11,0001209.05. 05:53
rfs4arm​v7l1 x 180080009.05. 05:59
r8s6arm​v7l1 x 150049809.05. 03:57
r5s7sarm​v7l1 x 15286409.05. 03:13
ras3sarm​v7l1 x 11,30084009.05. 04:29
r2s5ppc1 x 13966627.03. 13:43
r5s5sarm​v7l1 x 160060001.05. 15:04
r3s2riscv641 x 11,00028409.05. 02:11
r1s7arm​v6l1 x 11,00053009.05. 01:53
r5s7arm​v7l1 x 15286409.05. 03:11
r7s3arm​v6l1 x 1700509.05. 03:29
r9s1sarm​v7l1 x 101,25014.04. 18:03
r3s6x86_​641 x 11,6603,33309.05. 02:23
r5s5arm​v7l1 x 160059709.05. 03:08
ras4sarm​v7l1 x 160059707.02. 02:45
r3s5i5861 x 113326509.05. 02:20
r3s7i6861 x 15331,06609.05. 02:26
r4s5arm​v7l1 x 1500009.05. 02:46
r4s8arm​v7l1 x 140039809.05. 02:55
rbs2sx86_​641 x 13,500007.09. 15:06
ras6sarm​v7l1 x 11,0001,98709.05. 04:34
r9s8sarm​v7l1 x 180079609.05. 04:23
r2s2arm​v7l1 x 172049909.05. 01:58
r4s2sarm​v7l1 x 180053009.05. 02:36
r7s8arm​v7l1 x 11,00099509.05. 03:41
r5s6ppc1 x 153313309.05. 03:10
r7s4arm​v7l1 x 153634809.05. 03:34
r4s2arm​v7l1 x 180079609.05. 02:34
r4s3i5861 x 150099609.05. 02:39
r6s6i6861 x 11,6003,19109.05. 03:24
r2s6i6861 x 11,5002,99909.05. 02:01
r6s5i6861 x 11,5002,24409.05. 03:22
r2s8ppc1 x 14006609.05. 02:07
ras1i6861 x 11,4002,79909.05. 04:26
ras4arm​v7l1 x 150039809.05. 04:30
r4s3si6861 x 11,4662,93209.05. 02:41
r4s8sarm​v7l1 x 140039809.05. 02:56
rfs4sarm​v7l1 x 180080009.05. 06:06
r7s6arm​v7l1 x 11,00039828.02. 14:10
r8s1i5861 x 135070109.05. 03:45
r7s5i6861 x 11,3002,59309.05. 03:37
r2s1arm​v5tejl1 x 120019909.05. 01:57
r7s8sarm​v7l1 x 11,00059709.05. 03:43
r2s4mips​641 x 180053124.12. 13:46
ras7ppc1 x 13966508.05. 16:35
r9s4i6861 x 21,0003,99009.05. 04:11
rcs5x86_​642 x 12,80011,19809.05. 05:14
rbs6sx86_​642 x 11,3335,33209.05. 04:51
r1s4sarm​v7l2 x 14004809.05. 01:48
rcs3i6862 x 11,4005,58609.05. 05:06
rcs5sx86_​642 x 12,80011,19809.05. 05:16
r9s1x86_​642 x 12,0003,99209.05. 04:05
rcs2x86_​642 x 12,80011,23209.05. 05:05
rbs8arm​v7l2 x 16662,65009.05. 04:56
rcs4x86_​642 x 11,1004,37609.05. 05:11
r3s5sppc2 x 11,20040009.05. 02:22
r6s1x86_​642 x 12,0007,97809.05. 03:17
r6s4x86_​642 x 11,1004,37609.05. 03:21
r1s8i6861 x 21,6006,39809.05. 01:53
r1s4arm​v7l2 x 11,2004809.05. 01:47
r9s5sx86_​642 x 13,50013,99809.05. 04:19
r9s5x86_​642 x 12,70010,77413.07. 03:15
ras5arm​v7l2 x 11,0002409.05. 04:30
r9s4sx86_​642 x 11,3335,34709.05. 04:17
r8s7sx86_​642 x 13,30013,19809.05. 03:59
r4s7sx86_​642 x 11,8337,33209.05. 02:53
ras5sarm​v7l2 x 11,0002409.05. 04:31
r6s2x86_​642 x 11,6679,57809.05. 03:19
r8s7x86_​642 x 12,70010,77609.05. 03:58
r6s7i6862 x 12,3009,17611.01. 02:44
r8s8x86_​642 x 11,3005,14409.05. 04:01
r9s7arm​v7l2 x 11,000009.05. 04:21
ras2x86_​642 x 11,0674,26609.05. 04:27
r1s6x86_​642 x 22,13017,06409.05. 01:50
r6s8x86_​642 x 22,30018,35609.05. 03:25
r4s0x86_​642 x 22,30018,39609.05. 02:29
r8s2x86_​642 x 22,10016,76009.05. 03:47
r5s0x86_​642 x 22,20017,58209.05. 02:57
res5sx86_​642 x 22,20019,20009.05. 05:49
r9s6x86_​642 x 23,00023,94409.05. 04:20
rcs7x86_​642 x 21,80014,39609.05. 05:19
r1s6sx86_​642 x 21,66713,33209.05. 01:51
r5s4x86_​642 x 22,53020,26409.05. 03:04
r7s0x86_​642 x 22,30018,40009.05. 03:26
r8s2sx86_​642 x 22,10016,76009.05. 03:48
res5x86_​642 x 22,20019,20009.05. 05:47
ras0x86_​642 x 22,30018,41609.05. 04:25
r9s0x86_​642 x 22,30018,40009.05. 04:03
rbs0i6862 x 22,50017,60009.05. 04:37
r3s6sx86_​642 x 22,66721,33209.05. 02:25
r0s7sx86_​642 x 23,70029,52809.05. 01:36
r8s0x86_​642 x 22,30018,40009.05. 03:44
r1s1x86_​642 x 22,60021,69609.05. 01:42
r5s4sx86_​642 x 22,53020,26409.05. 03:05
r4s4ppc4 x 11,20049809.05. 02:42
r7s7sx86_​642 x 22,30018,39609.05. 03:40
r2s7saarch​644 x 11,50043209.05. 02:05
rds3x86_​644 x 11,91015,32409.05. 05:32
r2s6saarch​644 x 11,3506409.05. 02:02
rds4x86_​644 x 11,91015,32409.05. 05:34
rds2x86_​644 x 11,91015,32409.05. 05:31
res3x86_​644 x 12,00015,97209.05. 05:43
rbs6x86_​644 x 11,91515,32409.05. 04:49
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rbs3sarm​v7l4 x 11,40035609.05. 04:42
r7s7x86_​644 x 11,60012,76709.05. 03:38
r1s5aarch​644 x 11,20079609.05. 01:49
rbs7arm​v7l4 x 19961209.05. 04:52
r1s2sx86_​644 x 12,30028,00009.05. 01:45
rfs1aarch​644 x 11,50043209.05. 05:57
res1sx86_​644 x 11,60014,40009.05. 05:41
rds7x86_​644 x 11,60012,74809.05. 05:37
rfs2aarch​644 x 11,50043209.05. 05:58
r8s3x86_​644 x 12,66721,28009.05. 03:50
r2s0x86_​644 x 13,10024,80009.05. 01:55
r1s2x86_​644 x 12,30028,00009.05. 01:44
r4s7i6864 x 11,83314,66409.05. 02:52
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rds1x86_​644 x 11,91015,32409.05. 05:30
rds5x86_​644 x 11,60012,74809.05. 05:35
ras8x86_​644 x 11,60014,40009.05. 04:35
r9s3x86_​644 x 11,60012,74809.05. 04:08
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r9s2x86_​644 x 11,60012,74809.05. 04:06
r1s0x86_​644 x 13,10024,79609.05. 01:41
rcs7sx86_​644 x 11,50011,98009.05. 05:20
r1s8sx86_​644 x 11,90015,19609.05. 01:55
rds6x86_​644 x 11,60012,74809.05. 05:36
res8sx86_​644 x 11,90015,05209.05. 05:55
ras8sx86_​644 x 11,60012,74809.05. 04:36
r5s2x86_​644 x 12,70021,69909.05. 02:59
rbs4sx86_​644 x 11,60012,74809.05. 04:46
rcs4sx86_​644 x 11,1008,75209.05. 05:12
r1s3x86_​644 x 12,80022,42409.05. 01:46
res2x86_​644 x 11,60014,40009.05. 05:42
rbs3arm​v7l4 x 19962409.05. 04:41
r3s2sriscv644 x 1028409.05. 02:12
res8x86_​644 x 11,90015,05209.05. 05:54
res1x86_​644 x 11,60014,40009.05. 05:40
r7s3sarm​v7l4 x 11,40035609.05. 03:32
rds8x86_​644 x 11,60012,74809.05. 05:38
rbs4x86_​644 x 11,2009,60009.05. 04:44
r7s4sarm​v7l4 x 11,5001,08009.05. 03:36
rbs2x86_​644 x 12,00015,97209.05. 04:40
res4sx86_​644 x 11,90015,05209.05. 05:46
r4s5saarch​644 x 11,60020027.03. 14:13
res6x86_​644 x 11,1008,75209.05. 05:50
r5s3sx86_​644 x 11,60012,74809.05. 03:02
r4s1sarm​v7l4 x 11,5001,08009.05. 02:31
r7s1x86_​644 x 11,60012,84009.05. 03:28
rbs1x86_​644 x 12,00015,97209.05. 04:39
r4s1arm​v7l4 x 11,5001,08009.05. 02:30
r2s7aarch​644 x 12,40043209.05. 02:03
rbs7sarm​v7l4 x 19962409.05. 04:54
r9s3sx86_​644 x 13,00024,00009.05. 04:09
res4x86_​644 x 11,90015,05209.05. 05:45
res6saarch​644 x 101,60009.05. 05:51
rbs5saarch​644 x 11,6006409.05. 04:48
r3s4aarch​646 x 11,3009609.05. 02:15
r3s8i6866 x 13,20038,52609.05. 02:27
r5s1x86_​646 x 13,33340,09209.05. 02:57
rbs5i6864 x 2049,53909.05. 04:47
rcs6x86_​644 x 23,50063,99209.05. 05:17
r4s6x86_​644 x 23,40054,25609.05. 02:46
r8s5i6864 x 23,40054,40009.05. 03:55
r0s1x86_​644 x 22,30055,99209.05. 01:11
res0x86_​644 x 21,80031,99209.05. 05:39
r8s4sx86_​644 x 21,60028,80009.05. 03:53
rcs3sx86_​644 x 23,30052,69609.05. 05:08
rds0x86_​644 x 21,80031,99209.05. 05:29
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r0s3sx86_​644 x 23,60067,20009.05. 01:21
rbs8sx86_​644 x 22,40038,70409.05. 04:57
r5s3x86_​644 x 22,00031,87209.05. 03:00
r0s1sx86_​644 x 23,30052,67209.05. 01:12
r0s0x86_​644 x 22,50040,00009.05. 01:10
r0s2x86_​644 x 23,50055,86409.05. 01:13
r6s3x86_​644 x 22,20035,12009.05. 03:20
rcs8sx86_​644 x 23,30052,79209.05. 05:28
r8s4x86_​644 x 21,60028,80009.05. 03:52
r3s0i6864 x 23,50055,99209.05. 02:08
ras3aarch​648 x 12,0004,00009.05. 04:28
ras6aarch​648 x 12,0003,20009.05. 04:32
r0s2sx86_​6410 x 13,70073,99009.05. 01:15
r3s3x86_​646 x 23,33379,99209.05. 02:13
rcs1x86_​646 x 23,46783,37609.05. 05:03
r0s8sx86_​646 x 23,47083,38809.05. 01:40
r0s6x86_​648 x 23,600115,20009.05. 01:28
r0s4sx86_​648 x 23,600115,20009.05. 01:24
r0s5sx86_​648 x 23,600115,20009.05. 01:27
r0s4x86_​648 x 23,600115,20009.05. 01:22
r0s7x86_​648 x 23,600115,20009.05. 01:33
r0s8x86_​648 x 23,600115,20009.05. 01:38
r0s3x86_​648 x 23,600115,20009.05. 01:16
r0s5x86_​648 x 23,500115,20009.05. 01:25
rcs0x86_​648 x 22,40076,60009.05. 05:01
r0s6sx86_​6410 x 23,700147,98009.05. 01:30
rfs0x86_​6416 x 22,000128,00009.05. 05:57
rcs8x86_​6416 x 23,700217,15209.05. 05:26
r6s0x86_​642 x 10 x 21,700136,18009.05. 03:16
 

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