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2024-05-19 - 13:41

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00019.05. 13:10
r0s1x86_​644 x 22,30055,99219.05. 13:12
r0s1sx86_​644 x 23,30052,67219.05. 13:13
r0s2x86_​644 x 23,50055,86419.05. 13:14
r0s2sx86_​6410 x 13,70073,99019.05. 13:16
r0s3x86_​648 x 23,600115,20019.05. 13:17
r0s3sx86_​644 x 23,60067,20019.05. 13:22
r0s4x86_​648 x 23,600115,20019.05. 13:24
r0s4sx86_​648 x 23,600115,20019.05. 13:25
r0s5x86_​648 x 23,500115,20019.05. 13:27
r0s5sx86_​648 x 23,600115,20019.05. 13:29
r0s6x86_​648 x 23,600115,20019.05. 13:35
r0s6sx86_​6410 x 23,700147,98019.05. 13:36
r0s7x86_​648 x 23,600115,20019.05. 13:40
r0s7sx86_​642 x 23,70029,52819.05. 01:42
r0s8x86_​648 x 23,600115,20019.05. 01:44
r0s8sx86_​646 x 23,47083,38819.05. 01:46
r1s0x86_​644 x 13,10024,79619.05. 01:48
r1s1x86_​642 x 22,60021,69619.05. 01:50
r1s2x86_​644 x 12,30028,00019.05. 01:51
r1s2sx86_​644 x 12,30028,00019.05. 01:52
r1s3x86_​644 x 12,80022,42419.05. 01:54
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004819.05. 01:55
r1s4sarm​v7l2 x 14004819.05. 01:56
r1s5aarch​644 x 11,20079619.05. 01:57
r1s6x86_​642 x 22,13017,06419.05. 01:58
r1s6sx86_​642 x 21,66713,33219.05. 02:00
r1s7arm​v6l1 x 11,66753019.05. 02:01
r1s8i6861 x 21,6006,39819.05. 02:02
r1s8sx86_​644 x 11,90015,19619.05. 02:03
r2s0x86_​644 x 13,10024,80019.05. 02:04
r2s1arm​v5tejl1 x 120019919.05. 02:06
r2s2arm​v7l1 x 172049919.05. 02:06
r2s3arm​v7l0 x 1 x 162462419.05. 02:07
r2s3sarm​v7l0 x 1 x 16001,20019.05. 02:08
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99919.05. 02:09
r2s6saarch​644 x 11,3506419.05. 02:10
r2s7aarch​644 x 12,40043219.05. 02:11
r2s7saarch​644 x 11,50043219.05. 02:13
r2s8ppc1 x 14006619.05. 02:15
r3s0i6864 x 23,50055,99219.05. 02:17
r3s1i6864 x 12,40019,12719.05. 02:18
r3s2riscv641 x 11,00028419.05. 02:20
r3s2sriscv644 x 1028419.05. 02:22
r3s3x86_​646 x 23,33379,99219.05. 02:22
r3s4aarch​646 x 11,3009619.05. 02:25
r3s5i5861 x 113326519.05. 02:30
r3s5sppc2 x 11,20040019.05. 02:32
r3s6x86_​641 x 11,6603,33319.05. 02:33
r3s6sx86_​642 x 22,66721,33219.05. 02:35
r3s7i6861 x 15331,06619.05. 02:36
r3s8i6866 x 13,20038,52619.05. 02:37
r4s0x86_​642 x 22,30018,39619.05. 02:39
r4s1arm​v7l4 x 11,5001,08019.05. 02:40
r4s1sarm​v7l4 x 11,5001,08019.05. 02:42
r4s2arm​v7l1 x 180079619.05. 02:45
r4s2sarm​v7l1 x 180053019.05. 02:48
r4s3i5861 x 150099619.05. 02:52
r4s3si6861 x 11,4662,93219.05. 02:55
r4s4ppc4 x 11,20049819.05. 02:56
r4s5arm​v7l1 x 1500019.05. 03:00
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25619.05. 03:01
r4s6sarm​v7l0 x 1 x 11,0006619.05. 03:05
r4s7i6864 x 11,83314,66419.05. 03:07
r4s7sx86_​642 x 11,8337,33219.05. 03:09
r4s8arm​v7l1 x 140039819.05. 03:11
r4s8sarm​v7l1 x 140039819.05. 03:12
r5s0x86_​642 x 22,20017,58219.05. 03:13
r5s1x86_​646 x 13,33340,09219.05. 03:14
r5s2x86_​644 x 12,70021,69919.05. 03:15
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87219.05. 03:17
r5s3sx86_​644 x 11,60012,74819.05. 03:19
r5s4x86_​642 x 22,53020,26419.05. 03:21
r5s4sx86_​642 x 22,53020,26419.05. 03:22
r5s5arm​v7l1 x 160059719.05. 03:26
r5s5sarm​v7l1 x 160060019.05. 03:29
r5s6ppc1 x 153313319.05. 03:35
r5s7arm​v7l1 x 15286419.05. 03:36
r5s7sarm​v7l1 x 15286419.05. 03:38
r6s0x86_​642 x 10 x 21,700136,18019.05. 03:41
r6s1x86_​642 x 12,0007,97819.05. 03:42
r6s2x86_​642 x 11,6679,57819.05. 03:44
r6s3x86_​644 x 22,20035,12019.05. 03:45
r6s4x86_​642 x 11,1004,37619.05. 03:47
r6s5i6861 x 11,5002,99219.05. 03:49
r6s6i6861 x 11,6003,19119.05. 03:51
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35619.05. 03:52
r7s0x86_​642 x 22,30018,40019.05. 03:54
r7s1x86_​644 x 11,60012,84019.05. 03:55
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700519.05. 03:57
r7s3sarm​v7l4 x 11,40035619.05. 03:59
r7s4arm​v7l1 x 153634819.05. 04:02
r7s4sarm​v7l4 x 11,5001,08019.05. 04:05
r7s5i6861 x 11,3002,59319.05. 04:06
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76719.05. 04:07
r7s7sx86_​642 x 22,30018,39619.05. 04:08
r7s8arm​v7l1 x 11,00099519.05. 04:11
r7s8sarm​v7l1 x 11,00079619.05. 04:12
r8s0x86_​642 x 22,30018,40019.05. 04:13
r8s1i5861 x 135070119.05. 04:15
r8s2x86_​642 x 22,10016,76019.05. 04:17
r8s2sx86_​642 x 22,10016,76019.05. 04:19
r8s3x86_​644 x 12,66721,28019.05. 04:20
r8s4x86_​644 x 21,60028,80019.05. 04:22
r8s4sx86_​644 x 21,60028,80019.05. 04:23
r8s5i6864 x 23,40054,40019.05. 04:25
r8s6arm​v7l1 x 150049819.05. 04:26
r8s7x86_​642 x 12,70010,77619.05. 04:27
r8s7sx86_​642 x 13,30013,19819.05. 04:28
r8s8x86_​642 x 11,3005,14419.05. 04:30
r9s0x86_​642 x 22,30018,40019.05. 04:31
r9s1x86_​642 x 12,0003,99219.05. 04:33
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74819.05. 04:34
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74819.05. 04:36
r9s3sx86_​644 x 13,00024,00019.05. 04:37
r9s4i6861 x 21,0003,99019.05. 04:38
r9s4sx86_​642 x 11,3335,34719.05. 04:44
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99819.05. 04:46
r9s6x86_​642 x 23,00023,94419.05. 04:47
r9s7arm​v7l2 x 11,000019.05. 04:49
r9s8sarm​v7l1 x 180079619.05. 04:50
ras0x86_​642 x 22,30018,41619.05. 04:52
ras1i6861 x 11,4002,79919.05. 04:54
ras2x86_​642 x 11,0674,26619.05. 04:55
ras3aarch​648 x 12,0004,00019.05. 04:56
ras3sarm​v7l1 x 11,30084018.05. 17:03
ras4arm​v7l1 x 150039819.05. 04:57
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002419.05. 04:57
ras5sarm​v7l2 x 11,0002419.05. 04:59
ras6aarch​648 x 12,0003,20018.05. 17:06
ras6sarm​v7l1 x 11,0001,98719.05. 05:00
ras7ppc1 x 13966519.05. 05:01
ras8x86_​644 x 11,60014,40019.05. 05:02
ras8sx86_​644 x 11,60012,74819.05. 05:04
rbs0i6862 x 22,50017,60019.05. 05:05
rbs1x86_​644 x 12,00015,97219.05. 05:07
rbs2x86_​644 x 12,00015,97219.05. 05:08
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962818.05. 17:16
rbs3sarm​v7l4 x 11,40035619.05. 05:09
rbs4x86_​644 x 11,2009,60018.05. 17:19
rbs4sx86_​644 x 11,60012,74819.05. 05:12
rbs5i6864 x 2049,53919.05. 05:13
rbs5saarch​644 x 11,6006419.05. 05:14
rbs6x86_​644 x 11,91515,32419.05. 05:15
rbs6sx86_​642 x 11,3335,33219.05. 05:16
rbs7arm​v7l4 x 19962819.05. 05:18
rbs7sarm​v7l4 x 19962419.05. 05:19
rbs8arm​v7l2 x 16662,65019.05. 05:22
rbs8sx86_​644 x 22,40038,70419.05. 05:24
rcs0x86_​648 x 22,40076,60019.05. 05:27
rcs1x86_​646 x 23,46783,37619.05. 05:29
rcs2x86_​642 x 12,80011,23219.05. 05:31
rcs3i6862 x 11,4005,58619.05. 05:33
rcs3sx86_​644 x 23,30052,69619.05. 05:34
rcs4x86_​642 x 11,1004,37619.05. 05:37
rcs4sx86_​644 x 11,1008,75219.05. 05:39
rcs5x86_​642 x 12,80011,19819.05. 05:40
rcs5sx86_​642 x 12,80011,19819.05. 05:44
rcs6x86_​644 x 23,50063,99211.05. 17:51
rcs7x86_​642 x 21,80014,39619.05. 05:45
rcs7sx86_​644 x 11,50011,98019.05. 05:46
rcs8x86_​6416 x 23,700217,15219.05. 05:52
rcs8sx86_​644 x 23,30052,79219.05. 05:54
rds0x86_​644 x 21,80031,99219.05. 05:56
rds1x86_​644 x 11,91015,32419.05. 05:57
rds2x86_​644 x 11,91015,32419.05. 05:58
rds3x86_​644 x 11,91015,32419.05. 05:59
rds4x86_​644 x 11,91015,32419.05. 06:00
rds5x86_​644 x 11,60012,74819.05. 06:02
rds6x86_​644 x 11,60012,74819.05. 06:03
rds7x86_​644 x 11,60012,74819.05. 06:05
rds8x86_​644 x 11,60012,74819.05. 06:06
res0x86_​644 x 21,80031,99219.05. 06:06
res1x86_​644 x 11,60014,40019.05. 06:08
res1sx86_​644 x 11,60014,40019.05. 06:09
res2x86_​644 x 11,60014,40019.05. 06:10
res3x86_​644 x 12,00015,97219.05. 06:11
res3saarch​640 x 1 x 11,0001,60019.05. 06:13
res4x86_​644 x 11,90015,05219.05. 06:14
res4sx86_​644 x 11,90015,05219.05. 06:15
res5x86_​642 x 22,20019,20019.05. 06:16
res5sx86_​642 x 22,20019,20019.05. 06:18
res6x86_​644 x 11,1008,75219.05. 06:19
res6saarch​644 x 101,60019.05. 06:20
res7arm​v7l0 x 1 x 11,0001219.05. 06:22
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05219.05. 06:23
res8sx86_​644 x 11,90015,05219.05. 06:25
rfs0x86_​6416 x 22,000128,00019.05. 06:26
rfs1aarch​644 x 11,50043219.05. 06:27
rfs2aarch​644 x 11,50043219.05. 06:28
rfs4arm​v7l1 x 180080019.05. 06:28
rfs4sarm​v7l1 x 180080019.05. 06:36
rfs6arm​v7l1 x 16671,33219.05. 06:42
rfs6sarm​v7l1 x 16671,33219.05. 06:43
 

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