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2024-09-21 - 00:16

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00020.09. 13:10
r0s0sx86_​644 x 23,40054,39220.09. 13:10
r0s1x86_​644 x 22,30056,00020.09. 13:11
r0s1sx86_​644 x 23,30052,67220.09. 13:11
r0s2x86_​644 x 23,50055,86420.09. 13:11
r0s2sx86_​6410 x 13,70073,99020.09. 13:12
r0s3x86_​648 x 23,600115,20020.09. 13:13
r0s3sx86_​644 x 23,60067,20026.08. 01:14
r0s4x86_​648 x 23,600115,20020.09. 13:15
r0s4sx86_​648 x 23,600115,20020.09. 13:16
r0s5x86_​648 x 23,500115,20020.09. 13:16
r0s5sx86_​648 x 23,600115,20020.09. 01:16
r0s6x86_​648 x 23,600115,20020.09. 13:17
r0s6sx86_​6410 x 23,700147,98020.09. 13:18
r0s7x86_​648 x 23,600115,20020.09. 13:19
r0s7sx86_​642 x 23,70029,53226.08. 13:20
r0s8x86_​648 x 23,600115,20020.09. 13:20
r0s8sx86_​646 x 23,47083,37620.09. 13:21
r1s0x86_​644 x 13,10024,80020.09. 13:22
r1s1x86_​642 x 22,60021,69620.09. 13:22
r1s2x86_​644 x 12,30028,00020.09. 13:23
r1s2sx86_​644 x 12,30028,00020.09. 13:24
r1s3x86_​644 x 12,80022,42420.09. 13:25
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004820.09. 13:25
r1s4sarm​v7l2 x 14004820.09. 13:26
r1s5aarch​644 x 11,20079620.09. 13:27
r1s6x86_​642 x 22,13017,06420.09. 13:27
r1s6sx86_​642 x 21,66713,33220.09. 13:28
r1s7arm​v6l1 x 11,66753020.09. 13:28
r1s8i6861 x 21,6006,39820.09. 13:29
r1s8sx86_​644 x 11,90015,19620.09. 13:30
r2s0x86_​644 x 13,10024,80020.09. 13:30
r2s1arm​v5tejl1 x 120019920.09. 13:31
r2s2arm​v7l1 x 172049920.09. 13:31
r2s3arm​v7l0 x 1 x 162462420.09. 13:32
r2s3sarm​v7l0 x 1 x 16001,20020.09. 13:33
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966620.09. 13:33
r2s6i6861 x 11,5002,99920.09. 13:34
r2s6saarch​644 x 11,3506420.09. 13:35
r2s7aarch​644 x 12,40043220.09. 13:35
r2s7saarch​644 x 11,50043220.09. 13:36
r2s8ppc1 x 14006620.09. 13:37
r3s0i6864 x 23,50055,99220.09. 13:38
r3s1i6864 x 12,40019,12720.09. 13:38
r3s2riscv641 x 11,00028420.09. 13:39
r3s2sriscv644 x 1028420.09. 13:41
r3s3x86_​646 x 23,33379,99220.09. 13:41
r3s4aarch​646 x 11,3009620.09. 13:42
r3s5i5861 x 113326520.09. 13:43
r3s5sppc2 x 11,20040020.09. 13:45
r3s6x86_​641 x 21,6606,66620.09. 13:45
r3s6sx86_​642 x 22,66721,33220.09. 13:46
r3s7i6861 x 15331,06620.09. 13:46
r3s8i6866 x 13,20038,52620.09. 13:47
r4s0x86_​642 x 22,30018,39620.09. 13:48
r4s1arm​v7l4 x 11,50079220.09. 13:49
r4s1sarm​v7l4 x 11,5001,00820.09. 13:49
r4s2arm​v7l1 x 180079620.09. 13:51
r4s2sarm​v7l1 x 180053020.09. 13:52
r4s3i5861 x 150099620.09. 13:53
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049820.09. 13:55
r4s5arm​v7l1 x 1500020.09. 13:58
r4s5saarch​644 x 11,60020020.09. 13:58
r4s6x86_​644 x 23,40054,25620.09. 13:58
r4s6sarm​v7l0 x 1 x 11,0006620.09. 14:00
r4s7i6864 x 11,83314,66420.09. 14:01
r4s7sx86_​642 x 11,8337,33220.09. 14:02
r4s8arm​v7l1 x 140039820.09. 14:02
r4s8sarm​v7l1 x 140039820.09. 14:03
r5s0x86_​642 x 22,20017,58220.09. 14:04
r5s1x86_​646 x 13,33340,09220.09. 14:04
r5s2x86_​644 x 12,70021,69920.09. 14:05
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87220.09. 14:06
r5s3sx86_​644 x 11,60012,74820.09. 14:07
r5s4x86_​642 x 22,53020,26420.09. 14:07
r5s4sx86_​642 x 22,53020,26420.09. 14:08
r5s5arm​v7l1 x 160059720.09. 14:09
r5s5sarm​v7l1 x 160060020.09. 14:12
r5s6ppc1 x 153313320.09. 14:15
r5s7arm​v7l1 x 15286420.09. 14:15
r5s7sarm​v7l1 x 15284820.09. 14:17
r5s8x86_​644 x 12,00015,97220.09. 14:18
r6s0x86_​642 x 10 x 21,700136,18020.09. 14:19
r6s1x86_​642 x 12,0007,97820.09. 14:19
r6s2x86_​642 x 11,6679,57820.09. 14:20
r6s3x86_​644 x 22,20035,12020.09. 14:21
r6s4x86_​642 x 11,1004,37620.09. 14:21
r6s5i6861 x 11,5002,99220.09. 14:22
r6s6i6861 x 11,6003,19220.09. 14:23
r6s7i6862 x 12,3009,17620.09. 14:23
r6s8x86_​642 x 22,30018,35620.09. 14:24
r7s0x86_​642 x 22,30018,40020.09. 14:24
r7s1x86_​644 x 11,60012,84020.09. 14:25
r7s2aarch​642 x 11,7009620.09. 14:25
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700520.09. 14:26
r7s3sarm​v7l4 x 11,40035620.09. 14:28
r7s4arm​v7l1 x 153634820.09. 14:29
r7s4sarm​v7l4 x 11,5001,08020.09. 14:30
r7s5i6861 x 11,3002,59320.09. 14:31
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76720.09. 14:32
r7s7sx86_​642 x 22,30018,39620.09. 14:32
r7s8arm​v7l1 x 11,00099520.09. 14:33
r7s8sarm​v7l1 x 11,00079620.09. 14:34
r8s0x86_​642 x 22,30018,40020.09. 14:34
r8s1i5861 x 135070120.09. 14:35
r8s2x86_​642 x 22,10016,76020.09. 14:37
r8s2sx86_​642 x 22,10016,76020.09. 14:37
r8s3x86_​644 x 12,66721,28020.09. 14:38
r8s4x86_​644 x 21,60028,80020.09. 14:38
r8s4sx86_​644 x 21,60028,80020.09. 14:39
r8s5i6864 x 23,40054,40020.09. 14:39
r8s6arm​v7l1 x 150049820.09. 14:40
r8s6sx86_​644 x 13,30026,41620.09. 14:40
r8s7x86_​644 x 13,20025,49620.09. 14:41
r8s7sx86_​642 x 13,00011,98020.09. 14:41
r8s8x86_​642 x 11,3005,14420.09. 14:42
r9s0x86_​642 x 22,30018,39620.09. 14:42
r9s1x86_​642 x 12,0003,99220.09. 14:43
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74820.09. 14:44
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74820.09. 14:44
r9s3sx86_​644 x 13,00024,00020.09. 14:45
r9s4i6861 x 21,0003,99020.09. 14:46
r9s4sx86_​642 x 11,3335,34720.09. 14:51
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19820.09. 14:51
r9s6x86_​642 x 23,00023,94420.09. 14:52
r9s7arm​v7l2 x 11,000020.09. 14:52
r9s8sarm​v7l1 x 180079620.09. 14:53
ras0x86_​642 x 22,30018,41720.09. 14:54
ras1i6861 x 11,4002,79920.09. 14:54
ras2x86_​642 x 11,0674,26620.09. 14:55
ras2sx86_​644 x 11,90015,05220.09. 14:55
ras3aarch​648 x 12,0004,00020.09. 14:56
ras3sarm​v7l1 x 11,30084020.09. 14:56
ras4arm​v7l1 x 150039820.09. 14:57
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002420.09. 14:57
ras5sarm​v7l2 x 11,0002420.09. 14:58
ras6aarch​648 x 12,0003,20020.09. 14:58
ras6sarm​v7l1 x 11,0001,98720.09. 14:59
ras7ppc1 x 13966520.09. 14:59
ras8x86_​644 x 11,60014,40020.09. 15:00
ras8sx86_​644 x 11,60012,74820.09. 15:01
rbs0i6862 x 22,50017,60020.09. 15:01
rbs1x86_​644 x 12,00015,97220.09. 15:02
rbs2x86_​644 x 12,00015,97220.09. 15:02
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962420.09. 15:03
rbs3sarm​v7l4 x 11,40035620.09. 15:04
rbs4x86_​644 x 11,2009,60020.09. 15:05
rbs4sx86_​644 x 11,60012,74820.09. 15:05
rbs5i6864 x 2049,53920.09. 15:06
rbs5saarch​644 x 11,6006420.09. 15:06
rbs6x86_​644 x 11,91515,32420.09. 15:07
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961220.09. 15:07
rbs7sarm​v7l4 x 19962420.09. 15:08
rbs8arm​v7l2 x 16662,65020.09. 15:09
rbs8sx86_​644 x 22,40038,70420.09. 15:10
rcs0x86_​648 x 22,40076,60020.09. 15:11
rcs1x86_​646 x 23,46783,37620.09. 15:12
rcs2x86_​642 x 12,80011,23220.09. 15:13
rcs3i6862 x 11,4005,58620.09. 15:13
rcs3sx86_​644 x 13,30026,39620.09. 15:14
rcs4x86_​642 x 11,1004,37620.09. 15:14
rcs4sx86_​644 x 11,1008,75216.09. 03:07
rcs5x86_​642 x 12,80011,19820.09. 15:17
rcs5sx86_​642 x 12,80011,19820.09. 15:18
rcs6x86_​644 x 23,50063,99220.09. 15:18
rcs7x86_​642 x 21,80014,40020.09. 15:19
rcs7sx86_​644 x 11,50011,98020.09. 15:20
rcs8x86_​6416 x 23,700217,15220.09. 15:24
rcs8sx86_​644 x 23,30052,80020.09. 15:25
rds0x86_​644 x 21,80031,99220.09. 15:25
rds1x86_​644 x 11,91015,32420.09. 15:26
rds2x86_​644 x 11,91015,32420.09. 15:26
rds3x86_​644 x 11,91015,32420.09. 15:27
rds4x86_​644 x 11,91015,32420.09. 15:28
rds5x86_​644 x 11,60012,74820.09. 15:28
rds6x86_​644 x 11,60012,74820.09. 15:29
rds7x86_​644 x 11,60012,74820.09. 15:29
rds8x86_​644 x 11,60012,74820.09. 15:30
res0x86_​644 x 23,40054,39220.09. 15:31
res1x86_​644 x 11,60014,40020.09. 15:31
res1sx86_​644 x 11,60014,40020.09. 15:32
res2x86_​644 x 11,60014,40020.09. 15:32
res3x86_​644 x 12,00015,97220.09. 15:32
res3saarch​640 x 1 x 11,0001,60020.09. 15:33
res4x86_​644 x 11,90015,05220.09. 15:33
res4sx86_​644 x 11,90015,05220.09. 15:34
res5x86_​642 x 22,20019,20020.09. 15:35
res5sx86_​642 x 22,20019,20020.09. 15:35
res6x86_​644 x 11,1008,75220.09. 15:36
res6saarch​644 x 101,60020.09. 15:37
res7arm​v7l0 x 1 x 11,0001220.09. 15:37
res7sarm​v7l0 x 1 x 11,0001220.09. 15:38
res8x86_​644 x 11,90015,05220.09. 15:39
res8sx86_​644 x 11,90015,05220.09. 15:39
rfs0x86_​6416 x 22,000127,96820.09. 15:40
rfs1aarch​644 x 11,50043220.09. 15:40
rfs2aarch​644 x 11,50043220.09. 15:41
rfs3x86_​644 x 11,60012,74820.09. 15:41
rfs3sx86_​644 x 11,60012,74820.09. 15:42
rfs4arm​v7l1 x 180080020.09. 15:42
rfs4sarm​v7l1 x 180080020.09. 15:43
rfs6arm​v7l1 x 16671,33220.09. 15:44
rfs6sarm​v7l1 x 16671,33220.09. 15:45
rfs7x86_​644 x 22,60041,60020.09. 15:45
rfs7sx86_​644 x 17006,44820.09. 15:46
rfs8arm​v7l1 x 11,00012020.09. 15:47
 

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