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2024-05-05 - 11:25

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00005.05. 01:10
r0s1x86_​644 x 22,30055,99205.05. 01:11
r0s1sx86_​644 x 23,30052,67205.05. 01:12
r0s2x86_​644 x 23,50055,86405.05. 01:13
r0s2sx86_​6410 x 13,70073,99005.05. 01:15
r0s3x86_​648 x 23,600115,20005.05. 01:16
r0s3sx86_​644 x 23,60067,20005.05. 01:20
r0s4x86_​648 x 23,600115,20005.05. 01:22
r0s4sx86_​648 x 23,600115,20005.05. 01:24
r0s5x86_​648 x 23,500115,20005.05. 01:25
r0s5sx86_​648 x 23,600115,20005.05. 01:27
r0s6x86_​648 x 23,600115,20005.05. 01:31
r0s6sx86_​6410 x 23,700147,98005.05. 01:33
r0s7x86_​648 x 23,600115,20005.05. 01:36
r0s7sx86_​642 x 23,70029,52805.05. 01:40
r0s8x86_​648 x 23,600115,20005.05. 01:42
r0s8sx86_​646 x 23,47083,38805.05. 01:45
r1s0x86_​644 x 13,10024,79605.05. 01:46
r1s1x86_​642 x 22,60021,69605.05. 01:47
r1s2x86_​644 x 12,30028,00005.05. 01:49
r1s2sx86_​644 x 12,30028,00005.05. 01:50
r1s3x86_​644 x 12,80022,42405.05. 01:51
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004805.05. 01:53
r1s4sarm​v7l2 x 14004805.05. 01:54
r1s5aarch​644 x 11,20079605.05. 01:55
r1s6x86_​642 x 22,13017,06404.05. 13:52
r1s6sx86_​642 x 21,66713,33205.05. 01:56
r1s7arm​v6l1 x 11,66753005.05. 01:57
r1s8i6861 x 21,6006,39805.05. 01:58
r1s8sx86_​644 x 11,90015,19605.05. 02:00
r2s0x86_​644 x 13,10024,80005.05. 02:00
r2s1arm​v5tejl1 x 120019905.05. 04:02
r2s2arm​v7l1 x 172049905.05. 04:03
r2s3arm​v7l0 x 1 x 162462405.05. 04:04
r2s3sarm​v7l0 x 1 x 16001,20005.05. 04:05
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99905.05. 04:06
r2s6saarch​644 x 11,3506405.05. 04:07
r2s7aarch​644 x 12,40043205.05. 04:09
r2s7saarch​644 x 11,50043205.05. 04:11
r2s8ppc1 x 14006605.05. 04:12
r3s0i6864 x 23,50055,99205.05. 04:14
r3s1i6864 x 12,40019,12705.05. 04:15
r3s2riscv641 x 11,00028405.05. 04:17
r3s2sriscv644 x 1028405.05. 04:19
r3s3x86_​646 x 23,33379,99205.05. 04:20
r3s4aarch​646 x 11,3009605.05. 04:21
r3s5i5861 x 113326505.05. 04:26
r3s5sppc2 x 11,20040005.05. 04:28
r3s6x86_​641 x 11,6603,33305.05. 04:29
r3s6sx86_​642 x 22,66721,33205.05. 04:31
r3s7i6861 x 15331,06605.05. 04:32
r3s8i6866 x 13,20038,52605.05. 04:33
r4s0x86_​642 x 22,30018,39605.05. 04:35
r4s1arm​v7l4 x 11,50072005.05. 04:36
r4s1sarm​v7l4 x 11,50093605.05. 04:38
r4s2arm​v7l1 x 180079605.05. 04:41
r4s2sarm​v7l1 x 180053005.05. 04:43
r4s3i5861 x 150099605.05. 04:47
r4s3si6861 x 11,4662,93205.05. 04:49
r4s4ppc4 x 11,20049805.05. 04:50
r4s5arm​v7l1 x 1500005.05. 04:53
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25605.05. 04:55
r4s6sarm​v7l0 x 1 x 11,0006605.05. 04:59
r4s7i6864 x 11,83314,66405.05. 05:01
r4s7sx86_​642 x 11,8337,33205.05. 05:02
r4s8arm​v7l1 x 140039805.05. 05:04
r4s8sarm​v7l1 x 140039805.05. 05:05
r5s0x86_​642 x 22,20017,58205.05. 05:06
r5s1x86_​646 x 13,33340,09205.05. 05:07
r5s2x86_​644 x 12,70021,69905.05. 05:08
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87205.05. 05:10
r5s3sx86_​644 x 11,60012,74805.05. 05:12
r5s4x86_​642 x 22,53020,26405.05. 05:14
r5s4sx86_​642 x 22,53020,26405.05. 05:15
r5s5arm​v7l1 x 160059705.05. 05:19
r5s5sarm​v7l1 x 160060001.05. 15:04
r5s6ppc1 x 153313305.05. 05:24
r5s7arm​v7l1 x 15286405.05. 05:25
r5s7sarm​v7l1 x 15286405.05. 05:28
r6s0x86_​642 x 10 x 21,700136,18005.05. 05:30
r6s1x86_​642 x 12,0007,97805.05. 05:32
r6s2x86_​642 x 11,6679,57805.05. 05:34
r6s3x86_​644 x 22,20035,12004.05. 03:20
r6s4x86_​642 x 11,1004,37604.05. 03:21
r6s5i6861 x 11,5001,49605.05. 05:35
r6s6i6861 x 11,6003,19105.05. 05:37
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35605.05. 05:38
r7s0x86_​642 x 22,30018,40005.05. 05:40
r7s1x86_​644 x 11,60012,84005.05. 05:41
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700505.05. 05:43
r7s3sarm​v7l4 x 11,40035605.05. 05:45
r7s4arm​v7l1 x 153634805.05. 05:48
r7s4sarm​v7l4 x 11,5001,08005.05. 05:50
r7s5i6861 x 11,3002,59305.05. 05:51
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76705.05. 05:52
r7s7sx86_​642 x 22,30018,39605.05. 05:53
r7s8arm​v7l1 x 11,00099505.05. 05:55
r7s8sarm​v7l1 x 11,00079605.05. 05:57
r8s0x86_​642 x 22,30018,40005.05. 05:57
r8s1i5861 x 135070105.05. 05:59
r8s2x86_​642 x 22,10016,76005.05. 06:00
r8s2sx86_​642 x 22,10016,76005.05. 06:02
r8s3x86_​644 x 12,66721,28005.05. 06:03
r8s4x86_​644 x 21,60028,80005.05. 06:05
r8s4sx86_​644 x 21,60028,80005.05. 06:06
r8s5i6864 x 23,40054,40005.05. 06:07
r8s6arm​v7l1 x 150049805.05. 06:09
r8s7x86_​642 x 12,70010,77605.05. 06:10
r8s7sx86_​642 x 13,30013,19805.05. 06:11
r8s8x86_​642 x 11,3005,14405.05. 06:12
r9s0x86_​642 x 22,30018,40005.05. 06:14
r9s1x86_​642 x 12,0003,99205.05. 06:15
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74805.05. 06:16
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74805.05. 06:18
r9s3sx86_​644 x 13,00024,00005.05. 06:19
r9s4i6861 x 21,0003,99005.05. 06:21
r9s4sx86_​642 x 11,3335,34705.05. 06:26
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99805.05. 06:27
r9s6x86_​642 x 23,00023,94405.05. 06:29
r9s7arm​v7l2 x 11,000005.05. 06:31
r9s8sarm​v7l1 x 180079605.05. 06:32
ras0x86_​642 x 22,30018,41605.05. 06:33
ras1i6861 x 11,4002,79905.05. 06:34
ras2x86_​642 x 11,0674,26605.05. 06:35
ras3aarch​648 x 12,0004,00005.05. 06:36
ras3sarm​v7l1 x 11,30084005.05. 06:37
ras4arm​v7l1 x 150039805.05. 06:38
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002405.05. 06:39
ras5sarm​v7l2 x 11,0002405.05. 06:40
ras6aarch​648 x 12,0003,20005.05. 06:41
ras6sarm​v7l1 x 11,0001,98705.05. 06:43
ras7ppc1 x 13966505.05. 06:44
ras8x86_​644 x 11,60014,40005.05. 06:44
ras8sx86_​644 x 11,60012,74805.05. 06:46
rbs0i6862 x 22,50017,60005.05. 06:47
rbs1x86_​644 x 12,00015,97205.05. 06:49
rbs2x86_​644 x 23,20051,20005.05. 06:50
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962405.05. 06:51
rbs3sarm​v7l4 x 11,40035605.05. 06:52
rbs4x86_​644 x 11,2009,60005.05. 06:55
rbs4sx86_​644 x 11,60012,74805.05. 06:56
rbs5i6864 x 2049,53905.05. 06:57
rbs5saarch​644 x 11,6006405.05. 06:58
rbs6x86_​644 x 11,91515,32405.05. 06:59
rbs6sx86_​642 x 11,3335,33205.05. 07:01
rbs7arm​v7l4 x 19961205.05. 07:03
rbs7sarm​v7l4 x 19962405.05. 07:05
rbs8arm​v7l2 x 16662,65004.05. 17:11
rbs8sx86_​644 x 22,40038,70405.05. 07:07
rcs0x86_​648 x 22,40076,60005.05. 07:11
rcs1x86_​646 x 23,46783,37605.05. 07:12
rcs2x86_​642 x 12,80011,23205.05. 07:14
rcs3i6862 x 11,4005,58605.05. 07:15
rcs3sx86_​644 x 23,30052,69605.05. 07:17
rcs4x86_​642 x 11,1004,37605.05. 07:20
rcs4sx86_​644 x 11,1008,75205.05. 07:22
rcs5x86_​642 x 12,80011,19805.05. 07:23
rcs5sx86_​642 x 12,80011,19805.05. 07:26
rcs6x86_​644 x 23,50063,99205.05. 07:27
rcs7x86_​642 x 21,80014,39605.05. 07:29
rcs7sx86_​644 x 11,50011,98005.05. 07:30
rcs8x86_​6416 x 23,700217,15205.05. 07:36
rcs8sx86_​644 x 23,30052,79205.05. 07:38
rds0x86_​644 x 21,80031,99205.05. 07:39
rds1x86_​644 x 11,91015,32405.05. 07:41
rds2x86_​644 x 11,91015,32405.05. 07:42
rds3x86_​644 x 11,91015,32405.05. 07:43
rds4x86_​644 x 11,91015,32405.05. 07:44
rds5x86_​644 x 11,60012,74805.05. 07:46
rds6x86_​644 x 11,60012,74805.05. 07:47
rds7x86_​644 x 11,60012,74805.05. 07:48
rds8x86_​644 x 11,60012,74805.05. 07:49
res0x86_​644 x 21,80031,99205.05. 07:50
res1x86_​644 x 11,60014,40005.05. 07:52
res1sx86_​644 x 11,60014,40005.05. 07:53
res2x86_​644 x 11,60014,40005.05. 07:53
res3x86_​644 x 12,00015,97205.05. 07:55
res3saarch​640 x 1 x 11,0001,60005.05. 07:56
res4x86_​644 x 11,90015,05205.05. 07:57
res4sx86_​644 x 11,90015,05205.05. 07:59
res5x86_​642 x 22,20019,20005.05. 08:00
res5sx86_​642 x 22,20019,20005.05. 08:02
res6x86_​644 x 11,1008,75205.05. 08:03
res6saarch​644 x 101,60005.05. 08:05
res7arm​v7l0 x 1 x 11,0001205.05. 08:07
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05205.05. 08:08
res8sx86_​644 x 11,90015,05205.05. 08:10
rfs0x86_​6416 x 22,000128,00005.05. 08:11
rfs1aarch​644 x 11,50043205.05. 08:12
rfs2aarch​644 x 11,50043205.05. 08:12
rfs4arm​v7l1 x 180080005.05. 08:13
rfs4sarm​v7l1 x 180080005.05. 08:19
 

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