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2026-03-18 - 05:13

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50039,99218.03. 01:10
r0s0sx86_​644 x 23,40054,39218.03. 01:10
r0s1x86_​644 x 22,30056,00018.03. 01:11
r0s1sx86_​644 x 23,30052,80018.03. 01:11
r0s2x86_​644 x 23,50055,86418.03. 01:11
r0s2sx86_​6410 x 13,70073,99018.03. 01:12
r0s3x86_​648 x 23,600115,20018.03. 01:13
r0s3sx86_​644 x 23,60067,20018.03. 01:13
r0s4x86_​648 x 23,600115,20018.03. 01:14
r0s4sx86_​648 x 23,600115,20018.03. 01:15
r0s5x86_​648 x 23,500115,20018.03. 01:15
r0s5sx86_​648 x 23,600115,20018.03. 01:16
r0s6x86_​648 x 23,600115,20018.03. 01:16
r0s6sx86_​6410 x 23,700147,98018.03. 01:17
r0s7x86_​648 x 23,600115,20006.01. 13:20
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20014.03. 13:20
r0s8sx86_​646 x 23,47083,38818.03. 01:18
r1s0x86_​644 x 13,10024,80018.03. 01:19
r1s1x86_​642 x 22,60021,69618.03. 01:19
r1s2x86_​644 x 12,30027,99618.03. 01:20
r1s2sx86_​644 x 12,30028,00018.03. 01:20
r1s3x86_​644 x 12,80022,42418.03. 01:21
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004818.03. 01:22
r1s4sarm​v7l2 x 14004818.03. 01:22
r1s5aarch​644 x 11,20079618.03. 01:23
r1s6x86_​642 x 22,13017,06418.03. 01:23
r1s6sx86_​642 x 21,66713,33218.03. 01:24
r1s7arm​v6l1 x 11,66753018.03. 01:24
r1s8i6861 x 21,6006,40018.03. 01:25
r1s8sx86_​644 x 11,90015,19618.03. 01:25
r2s0x86_​644 x 13,10024,79618.03. 01:26
r2s1arm​v5tejl1 x 120019918.03. 01:26
r2s2arm​v7l1 x 172049918.03. 01:27
r2s3arm​v7l0 x 1 x 162462418.03. 01:27
r2s3sarm​v7l0 x 2 x 16001,20018.03. 01:28
r2s4mips​641 x 180053129.09. 13:34
r2s5ppc1 x 13966625.12. 13:33
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r2s6i6861 x 11,5002,99918.03. 01:29
r2s6saarch​644 x 11,3506418.03. 01:30
r2s7aarch​644 x 12,40043218.03. 01:30
r2s7saarch​644 x 11,50043218.03. 01:31
r2s8ppc1 x 14006618.03. 01:31
r3s0i6864 x 23,50055,99218.03. 01:32
r3s1i6864 x 12,40019,12818.03. 01:33
r3s2riscv641 x 11,00028418.03. 01:33
r3s2sriscv644 x 1028418.03. 01:34
r3s3x86_​646 x 23,33379,99218.03. 01:34
r3s3sx86_​644 x 13,40011,98018.03. 01:35
r3s4aarch​646 x 11,3009618.03. 01:36
r3s5i5861 x 113326518.03. 01:36
r3s5sppc2 x 11,20040018.03. 01:38
r3s6x86_​641 x 21,6606,66618.03. 01:38
r3s6sx86_​642 x 22,66721,33218.03. 01:39
r3s7i6861 x 15331,06618.03. 01:40
r3s8i6864 x 13,20027,36614.03. 13:46
r4s0x86_​642 x 22,30018,40018.03. 01:41
r4s1arm​v7l4 x 11,50072018.03. 01:42
r4s1sarm​v7l4 x 11,5001,00818.03. 01:42
r4s2arm​v7l1 x 180079618.03. 01:43
r4s2sarm​v7l1 x 180053018.03. 01:44
r4s3i5861 x 150099618.03. 01:46
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049818.03. 01:47
r4s5arm​v7l1 x 1500018.03. 01:51
r4s5saarch​644 x 11,60020018.03. 01:51
r4s6x86_​644 x 23,40054,25618.03. 01:51
r4s6sarm​v7l0 x 1 x 11,0006618.03. 01:52
r4s7i6864 x 11,83314,66418.03. 01:53
r4s7sx86_​642 x 11,8337,33218.03. 01:53
r4s8arm​v7l1 x 140039818.03. 01:54
r4s8sarm​v7l1 x 140039818.03. 01:55
r5s0x86_​642 x 22,20017,58418.03. 01:55
r5s1x86_​646 x 13,33340,08618.03. 01:55
r5s2x86_​644 x 12,70021,69918.03. 01:56
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87218.03. 01:57
r5s3sx86_​644 x 11,60012,74818.03. 01:57
r5s4x86_​642 x 22,53020,26418.03. 01:58
r5s4sx86_​644 x 11,60012,74818.03. 01:59
r5s5arm​v7l1 x 160059718.03. 02:01
r5s5sarm​v7l1 x 160060018.03. 02:03
r5s6ppc1 x 153313318.03. 02:06
r5s7arm​v7l1 x 15286418.03. 02:07
r5s7sarm​v7l1 x 15286418.03. 02:08
r5s8x86_​644 x 12,00015,97218.03. 02:10
r6s0x86_​642 x 10 x 21,700136,14018.03. 02:10
r6s1x86_​642 x 12,0007,97812.12. 02:21
r6s2x86_​642 x 11,6679,57818.03. 02:11
r6s3x86_​644 x 22,20035,12018.03. 02:11
r6s4x86_​642 x 11,1004,37618.03. 02:12
r6s5i6861 x 11,5002,99218.03. 02:13
r6s6i6861 x 11,6003,19218.03. 02:14
r6s7i6862 x 12,3009,17618.03. 02:14
r6s8x86_​642 x 22,30018,35618.03. 02:15
r7s0x86_​642 x 22,30018,40018.03. 02:16
r7s1x86_​644 x 11,60012,83918.03. 02:16
r7s2aarch​642 x 11,7009618.03. 02:16
r7s2sriscv644 x 1028418.03. 02:17
r7s3arm​v6l1 x 1700518.03. 02:18
r7s3sarm​v7l4 x 11,40035618.03. 02:20
r7s4arm​v7l1 x 153634818.03. 02:21
r7s4sarm​v7l4 x 11,5001,08018.03. 02:22
r7s5i6861 x 11,3002,59318.03. 02:22
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76718.03. 02:23
r7s7sx86_​642 x 22,30018,39618.03. 02:23
r7s8arm​v7l1 x 11,00099518.03. 02:24
r7s8sarm​v7l1 x 11,00099618.03. 02:25
r8s0x86_​642 x 22,30018,40018.03. 02:25
r8s1i5861 x 135070118.03. 02:26
r8s3x86_​644 x 12,66721,28018.03. 02:27
r8s4x86_​644 x 21,60028,80018.03. 02:28
r8s4sx86_​644 x 21,60028,80018.03. 02:28
r8s5i6864 x 23,40054,40018.03. 02:29
r8s6arm​v7l1 x 150049818.03. 02:29
r8s6sx86_​644 x 13,30026,41618.03. 02:30
r8s7x86_​644 x 13,20025,49618.03. 02:30
r8s7sx86_​642 x 13,00011,98018.03. 02:31
r8s8x86_​642 x 11,3005,14418.03. 02:31
r9s0x86_​644 x 23,60057,60018.03. 02:32
r9s1x86_​642 x 12,0007,98412.02. 14:30
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74818.03. 02:33
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74818.03. 02:34
r9s3sx86_​644 x 13,00024,00018.03. 02:34
r9s4i6861 x 21,0003,99018.03. 02:35
r9s4sx86_​642 x 11,3335,34718.03. 02:35
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19818.03. 02:36
r9s6x86_​642 x 23,00023,94418.03. 02:37
r9s7arm​v7l2 x 11,000018.03. 02:37
r9s8sarm​v7l1 x 180079618.03. 02:38
ras0x86_​642 x 22,30018,41818.03. 02:39
ras1i6861 x 11,4002,79918.03. 02:39
ras2x86_​642 x 11,0674,26618.03. 02:40
ras2sx86_​644 x 11,90015,05218.03. 02:40
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084018.03. 02:41
ras4aarch​648 x 12,40038418.03. 02:41
ras4saarch​648 x 12,40038429.09. 03:02
ras5arm​v7l2 x 11,0002418.03. 02:42
ras5sarm​v7l2 x 11,0002418.03. 02:42
ras6aarch​648 x 12,0003,20018.03. 02:42
ras6sarm​v7l1 x 11,0001,98718.03. 02:43
ras7ppc1 x 13966518.03. 02:44
ras8x86_​644 x 11,60014,40018.03. 02:44
ras8sx86_​644 x 11,60012,74818.03. 02:44
rbs0i6862 x 22,50017,60018.03. 02:45
thlfw2x86_​644 x 12,00015,97214.03. 14:50
thlfwx86_​644 x 12,00015,97214.03. 14:51
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962418.03. 02:46
rbs3sarm​v7l4 x 11,40035618.03. 02:46
rbs4x86_​644 x 11,2009,60018.03. 02:47
rbs4sx86_​644 x 11,60012,74818.03. 02:47
rbs5i6864 x 2052,36518.03. 02:48
rbs5saarch​644 x 11,6006418.03. 02:48
rbs6x86_​644 x 11,91515,32418.03. 02:48
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961218.03. 02:49
rbs7sarm​v7l4 x 19962418.03. 02:51
rbs8arm​v7l2 x 16662,65018.03. 02:52
rbs8sx86_​644 x 22,40038,70418.03. 02:53
rcs0x86_​648 x 22,40076,40018.03. 02:54
rcs1x86_​646 x 23,46783,37618.03. 02:55
rcs2x86_​642 x 12,80011,23218.03. 02:56
rcs3i6862 x 11,4005,58618.03. 02:56
rcs3sx86_​644 x 13,30026,39618.03. 02:57
rcs4x86_​642 x 11,1004,37618.03. 02:58
rcs5x86_​642 x 12,80011,19818.03. 02:59
rcs5sx86_​642 x 12,80011,19818.03. 03:01
rcs6x86_​644 x 23,50063,99218.03. 03:01
rcs7x86_​642 x 21,80014,40018.03. 03:02
rcs7sx86_​644 x 11,50011,98017.03. 15:03
rcs8x86_​6416 x 23,700217,18418.03. 03:03
rcs8sx86_​644 x 23,30052,80017.03. 15:08
rds0x86_​644 x 21,80031,99218.03. 03:04
rds1x86_​644 x 11,60012,74818.03. 03:04
rds2x86_​644 x 11,60012,74818.03. 03:05
rds3x86_​644 x 11,60012,74818.03. 03:06
rds4x86_​644 x 11,60012,74818.03. 03:06
rds5x86_​644 x 11,60012,74818.03. 03:07
rds6x86_​644 x 11,60012,74818.03. 03:07
rds7x86_​644 x 11,60012,74818.03. 03:08
rds8x86_​644 x 11,60012,74818.03. 03:08
res0x86_​644 x 23,40054,39218.03. 03:09
res1x86_​644 x 11,60014,40018.03. 03:10
res1sx86_​644 x 11,60014,40018.03. 03:10
res2x86_​644 x 11,60014,40018.03. 03:11
res3x86_​644 x 12,00015,97218.03. 03:11
res3saarch​640 x 1 x 11,0001,60018.03. 03:12
res4x86_​644 x 11,90015,05218.03. 03:12
res4sx86_​644 x 11,90015,05218.03. 03:13
res5x86_​642 x 22,20019,20018.03. 03:14
res5sx86_​642 x 22,20019,20018.03. 03:14
res6x86_​644 x 11,1008,75218.03. 03:15
res6saarch​644 x 101,60018.03. 03:16
res7arm​v7l0 x 1 x 11,0001218.03. 03:16
res7sarm​v7l0 x 1 x 11,0001218.03. 03:17
res8x86_​644 x 11,90015,05218.03. 03:18
res8sx86_​644 x 11,90015,05218.03. 03:19
rfs0x86_​6416 x 22,000128,00018.03. 03:20
rfs1aarch​644 x 11,50043218.03. 03:20
rfs1saarch​644 x 11,50043218.03. 03:20
rfs2x86_​644 x 13,00024,00018.03. 03:21
rfs2sx86_​642 x 13,00011,99818.03. 03:21
rfs3x86_​644 x 11,60012,74818.03. 03:21
rfs3sx86_​644 x 11,60012,74818.03. 03:22
rfs4aarch​641 x 11,4001,60018.03. 03:22
rfs4sarm​v7l1 x 180080018.03. 03:23
rfs5aarch​644 x 11,2006418.03. 03:25
rfs5saarch​644 x 11,2006418.03. 03:26
rfs6arm​v7l1 x 16671,33218.03. 03:27
rfs6sarm​v7l1 x 16671,33218.03. 03:27
rfs7x86_​644 x 22,60041,60018.03. 03:28
rfs7sx86_​644 x 17006,44818.03. 03:28
rfs8arm​v7l1 x 11,00012018.03. 03:29
 

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