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2025-07-14 - 00:39

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00013.07. 13:10
r0s0sx86_​644 x 23,40054,39213.07. 13:10
r0s1x86_​644 x 22,30056,00013.07. 13:11
r0s1sx86_​644 x 23,30052,79213.07. 13:11
r0s2x86_​644 x 23,50055,86413.07. 13:11
r0s2sx86_​6410 x 13,70073,99013.07. 13:12
r0s3x86_​648 x 23,600115,20013.07. 13:13
r0s3sx86_​644 x 23,60067,20013.07. 13:15
r0s4x86_​648 x 23,600115,20013.07. 13:16
r0s4sx86_​648 x 23,600115,20013.07. 13:16
r0s5x86_​648 x 23,500115,20013.07. 13:17
r0s5sx86_​648 x 23,600115,20013.07. 13:18
r0s6x86_​648 x 23,600115,20028.02. 13:18
r0s6sx86_​6410 x 23,700147,98013.07. 13:19
r0s7x86_​648 x 23,600115,20013.07. 13:20
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20013.07. 13:21
r0s8sx86_​646 x 23,47083,37613.07. 13:22
r1s0x86_​644 x 13,10024,80013.07. 13:23
r1s1x86_​642 x 22,60021,69613.07. 13:24
r1s2x86_​644 x 12,30028,00013.07. 13:24
r1s2sx86_​644 x 12,30028,00013.07. 13:25
r1s3x86_​644 x 12,80022,42413.07. 13:25
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004813.07. 13:26
r1s4sarm​v7l2 x 14004813.07. 13:27
r1s5aarch​644 x 11,20079613.07. 13:27
r1s6x86_​642 x 22,13017,06413.07. 13:28
r1s6sx86_​642 x 21,66713,33213.07. 13:28
r1s7arm​v6l1 x 11,66753013.07. 13:29
r1s8i6861 x 21,6006,39813.07. 13:29
r1s8sx86_​644 x 11,90015,19613.07. 13:30
r2s0x86_​644 x 13,10024,80013.07. 13:31
r2s1arm​v5tejl1 x 120019913.07. 13:31
r2s2arm​v7l1 x 172049913.07. 13:35
r2s3arm​v7l0 x 1 x 162462413.07. 13:35
r2s3sarm​v7l0 x 2 x 16001,20013.07. 13:36
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966613.07. 13:37
r2s5sarm​v7l4 x 11,20015213.07. 13:37
r2s6i6861 x 11,5002,99913.07. 13:39
r2s6saarch​644 x 11,3506413.07. 13:39
r2s7aarch​644 x 12,40043213.07. 13:40
r2s7saarch​644 x 11,50043213.07. 13:41
r2s8ppc1 x 14006613.07. 13:41
r3s0i6864 x 23,50055,99213.07. 13:42
r3s1i6864 x 12,40019,12713.07. 13:43
r3s2riscv641 x 11,00028413.07. 13:43
r3s2sriscv644 x 1028413.07. 13:44
r3s3x86_​646 x 23,33380,00413.07. 13:45
r3s3sx86_​644 x 13,40011,98013.07. 13:45
r3s4aarch​646 x 11,3009613.07. 13:46
r3s5i5861 x 113326513.07. 13:47
r3s5sppc2 x 11,20040013.07. 13:48
r3s6x86_​641 x 21,6606,66613.07. 13:49
r3s6sx86_​642 x 22,66721,33213.07. 13:50
r3s7i6861 x 15331,06613.07. 13:50
r3s8i6864 x 13,20027,36513.07. 13:51
r4s0x86_​642 x 22,30018,40013.07. 13:52
r4s1arm​v7l4 x 11,50079213.07. 13:53
r4s1sarm​v7l4 x 11,50086413.07. 13:53
r4s2arm​v7l1 x 180079613.07. 13:54
r4s2sarm​v7l1 x 180053013.07. 13:55
r4s3i5861 x 150099613.07. 13:57
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049813.07. 13:58
r4s5arm​v7l1 x 1500013.07. 14:02
r4s5saarch​644 x 11,60020013.07. 14:02
r4s6x86_​644 x 23,40054,25613.07. 14:02
r4s6sarm​v7l0 x 1 x 11,0006613.07. 14:04
r4s7i6864 x 11,83314,66413.07. 14:05
r4s7sx86_​642 x 11,8337,33213.07. 14:05
r4s8arm​v7l1 x 140039813.07. 14:06
r4s8sarm​v7l1 x 140039813.07. 14:07
r5s0x86_​642 x 22,20017,58213.07. 14:07
r5s1x86_​648 x 13,33353,44813.07. 14:08
r5s2x86_​644 x 12,70021,69913.07. 14:08
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87213.07. 14:09
r5s3sx86_​644 x 11,60012,74813.07. 14:10
r5s4x86_​642 x 22,53020,26413.07. 14:11
r5s4sx86_​642 x 22,53020,26413.07. 14:11
r5s5arm​v7l1 x 160059713.07. 14:12
r5s5sarm​v7l1 x 160060013.07. 14:14
r5s6ppc1 x 153313313.07. 14:17
r5s7arm​v7l1 x 15286413.07. 14:18
r5s7sarm​v7l1 x 15284813.07. 14:19
r5s8x86_​644 x 12,00015,97213.07. 14:21
r6s0x86_​642 x 10 x 21,700136,18013.07. 14:21
r6s1x86_​642 x 12,0007,97813.07. 14:22
r6s2x86_​642 x 11,6679,57813.07. 14:22
r6s3x86_​644 x 22,20035,12013.07. 14:23
r6s4x86_​642 x 11,1004,37613.07. 14:24
r6s5i6861 x 11,5001,12213.07. 14:47
r6s6i6861 x 11,6003,19213.07. 14:48
r6s7i6862 x 12,3009,17613.07. 14:49
r6s8x86_​642 x 22,30018,35613.07. 14:49
r7s0x86_​642 x 22,30018,40013.07. 14:50
r7s1x86_​644 x 11,60012,83913.07. 14:51
r7s2aarch​642 x 11,7009613.07. 14:51
r7s2sriscv644 x 1028413.07. 14:51
r7s3arm​v6l1 x 1700513.07. 14:53
r7s3sarm​v7l4 x 11,40035613.07. 14:54
r7s4arm​v7l1 x 153634813.07. 14:55
r7s4sarm​v7l4 x 11,5001,08013.07. 14:56
r7s5i6861 x 11,3002,59313.07. 14:56
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76713.07. 14:57
r7s7sx86_​642 x 22,30018,39613.07. 14:58
r7s8arm​v7l1 x 11,00099513.07. 14:59
r7s8sarm​v7l1 x 11,00099613.07. 14:59
r8s0x86_​642 x 22,30018,40013.07. 15:00
r8s1i5861 x 135070113.07. 15:01
r8s3x86_​644 x 12,66721,28013.07. 15:02
r8s4x86_​644 x 21,60028,80013.07. 15:02
r8s4sx86_​644 x 21,60028,80013.07. 15:03
r8s5i6864 x 23,40054,40013.07. 15:04
r8s6arm​v7l1 x 150049813.07. 15:04
r8s6sx86_​644 x 13,30026,41613.07. 15:05
r8s7x86_​644 x 13,20025,49613.07. 15:06
r8s7sx86_​642 x 13,00011,98013.07. 15:06
r8s8x86_​642 x 11,3005,14413.07. 15:06
r9s0x86_​644 x 23,60057,60013.07. 15:07
r9s1x86_​642 x 12,0003,99213.07. 15:08
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74813.07. 15:09
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74813.07. 15:09
r9s3sx86_​644 x 13,00024,00013.07. 15:10
r9s4i6861 x 21,0003,99013.07. 15:11
r9s4sx86_​642 x 11,3335,34713.07. 15:11
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19813.07. 15:12
r9s6x86_​642 x 23,00023,94413.07. 15:13
r9s7arm​v7l2 x 11,000013.07. 15:13
r9s8sarm​v7l1 x 180079613.07. 15:14
ras0x86_​642 x 22,30018,41813.07. 15:15
ras1i6861 x 11,4002,79913.07. 15:15
ras2x86_​642 x 11,0674,26613.07. 15:16
ras2sx86_​644 x 11,90015,05213.07. 15:16
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084013.07. 15:17
ras4arm​v7l1 x 150039808.05. 14:49
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002413.07. 15:17
ras5sarm​v7l2 x 11,0002413.07. 15:18
ras6aarch​648 x 12,0003,20013.07. 15:18
ras6sarm​v7l1 x 11,0001,98713.07. 15:19
ras7ppc1 x 13966513.07. 15:20
ras8x86_​644 x 11,60014,40013.07. 15:21
ras8sx86_​644 x 11,60012,74813.07. 15:21
rbs0i6862 x 22,50017,60013.07. 15:21
rbs1x86_​644 x 12,00015,97213.07. 15:22
rbs2x86_​644 x 12,00015,97213.07. 15:22
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962413.07. 15:23
rbs3sarm​v7l4 x 11,40035613.07. 15:23
rbs4x86_​644 x 11,2009,60013.07. 15:24
rbs4sx86_​644 x 11,60012,74813.07. 15:25
rbs5i6864 x 2049,41513.07. 15:26
rbs5saarch​644 x 11,6006413.07. 15:26
rbs6x86_​644 x 11,91515,32413.07. 15:26
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961213.07. 15:27
rbs7sarm​v7l4 x 19962413.07. 15:29
rbs8arm​v7l2 x 16662,65013.07. 15:30
rbs8sx86_​644 x 22,40038,70413.07. 15:31
rcs0x86_​648 x 22,40076,60813.07. 15:32
rcs1x86_​646 x 23,46783,37613.07. 15:33
rcs2x86_​642 x 12,80011,23213.07. 15:34
rcs3i6862 x 11,4005,58613.07. 15:34
rcs3sx86_​644 x 13,30026,39613.07. 15:35
rcs4x86_​642 x 11,1004,37613.07. 15:36
rcs5x86_​642 x 12,80011,19813.07. 15:37
rcs5sx86_​642 x 12,80011,19813.07. 15:39
rcs6x86_​644 x 23,50063,99213.07. 15:39
rcs7x86_​642 x 21,80014,40013.07. 15:40
rcs7sx86_​644 x 11,50011,98013.07. 15:41
rcs8x86_​6416 x 23,700217,15213.07. 15:44
rcs8sx86_​644 x 23,30052,80013.07. 15:45
rds0x86_​644 x 21,80031,99213.07. 15:46
rds1x86_​644 x 11,60012,74813.07. 15:46
rds2x86_​644 x 11,60012,74813.07. 15:47
rds3x86_​644 x 11,60012,74813.07. 15:47
rds4x86_​644 x 11,60012,74813.07. 15:48
rds5x86_​644 x 11,60012,74813.07. 15:48
rds6x86_​644 x 11,60012,74813.07. 15:49
rds7x86_​644 x 11,60012,74813.07. 15:50
rds8x86_​644 x 11,60012,74813.07. 15:50
res0x86_​644 x 23,40054,39213.07. 15:51
res1x86_​644 x 11,60014,40013.07. 15:52
res1sx86_​644 x 11,60014,40013.07. 15:52
res2x86_​644 x 11,60014,40013.07. 15:52
res3x86_​644 x 12,00015,97213.07. 15:53
res3saarch​640 x 1 x 11,0001,60013.07. 15:54
res4x86_​644 x 11,90015,05213.07. 15:54
res4sx86_​644 x 11,90015,05213.07. 15:55
res5x86_​642 x 22,20019,20013.07. 15:56
res5sx86_​642 x 22,20019,20013.07. 15:56
res6x86_​644 x 11,1008,75213.07. 15:57
res6saarch​644 x 101,60013.07. 15:57
res7arm​v7l0 x 1 x 11,0001213.07. 15:58
res7sarm​v7l0 x 1 x 11,0001213.07. 15:59
res8x86_​644 x 11,90015,05213.07. 15:59
res8sx86_​644 x 11,90015,05213.07. 16:00
rfs0x86_​6416 x 22,000127,96813.07. 16:01
rfs1aarch​644 x 11,50043213.07. 16:01
rfs1saarch​644 x 11,50043213.07. 16:02
rfs2x86_​644 x 13,00023,99613.07. 16:02
rfs2sx86_​642 x 13,00011,99813.07. 16:02
rfs3x86_​644 x 11,60012,74813.07. 16:02
rfs3sx86_​644 x 11,60012,74813.07. 16:03
rfs4arm​v7l1 x 180080013.07. 16:04
rfs4sarm​v7l1 x 180080013.07. 16:05
rfs5aarch​644 x 11,2006413.07. 16:07
rfs5saarch​644 x 11,2006410.07. 16:03
rfs6arm​v7l1 x 16671,33213.07. 16:07
rfs6sarm​v7l1 x 16671,33213.07. 16:08
rfs7x86_​644 x 22,60041,60013.07. 16:08
rfs7sx86_​644 x 17006,44813.07. 16:09
rfs8arm​v7l1 x 11,00012004.03. 03:47
 

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