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2024-06-02 - 09:15

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00002.06. 01:10
r0s1x86_​644 x 22,30055,99202.06. 01:11
r0s1sx86_​644 x 23,30052,67202.06. 01:12
r0s2x86_​644 x 23,50055,86402.06. 01:15
r0s2sx86_​6410 x 13,70073,99002.06. 01:16
r0s3x86_​648 x 23,600115,20002.06. 01:18
r0s3sx86_​644 x 23,60067,20002.06. 01:23
r0s4x86_​648 x 23,600115,20002.06. 01:25
r0s4sx86_​648 x 23,600115,20002.06. 01:27
r0s5x86_​648 x 23,500115,20002.06. 01:30
r0s5sx86_​648 x 23,600115,20002.06. 01:31
r0s6x86_​648 x 23,600115,20002.06. 01:35
r0s6sx86_​6410 x 23,700147,98002.06. 01:37
r0s7x86_​648 x 23,600115,20002.06. 01:41
r0s7sx86_​642 x 23,70029,52802.06. 01:46
r0s8x86_​648 x 23,600115,20002.06. 01:48
r0s8sx86_​646 x 23,47083,38802.06. 01:51
r1s0x86_​644 x 13,10024,80002.06. 01:52
r1s1x86_​642 x 22,60021,69602.06. 01:54
r1s2x86_​644 x 12,30028,00002.06. 01:56
r1s2sx86_​644 x 12,30028,00002.06. 01:58
r1s3x86_​644 x 12,80022,42402.06. 02:00
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004802.06. 02:02
r1s4sarm​v7l2 x 14004802.06. 02:03
r1s5aarch​644 x 11,20079602.06. 02:04
r1s6x86_​642 x 22,13017,06402.06. 02:05
r1s6sx86_​642 x 21,66713,33202.06. 02:06
r1s7arm​v6l1 x 11,66753002.06. 02:08
r1s8i6861 x 21,6006,39802.06. 02:09
r1s8sx86_​644 x 11,90015,19602.06. 02:10
r2s0x86_​644 x 13,10024,80002.06. 02:11
r2s1arm​v5tejl1 x 120019902.06. 02:12
r2s2arm​v7l1 x 172049902.06. 02:13
r2s3arm​v7l0 x 1 x 162462402.06. 02:14
r2s3sarm​v7l0 x 1 x 16001,20001.06. 14:16
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99902.06. 02:16
r2s6saarch​644 x 11,3506402.06. 02:17
r2s7aarch​644 x 12,40043202.06. 02:18
r2s7saarch​644 x 11,50043202.06. 02:21
r2s8ppc1 x 14006602.06. 02:22
r3s0i6864 x 23,50055,99202.06. 02:24
r3s1i6864 x 12,40019,12702.06. 02:25
r3s2riscv641 x 11,00028402.06. 02:26
r3s2sriscv644 x 1028402.06. 02:28
r3s3x86_​646 x 23,33379,99202.06. 02:29
r3s4aarch​646 x 11,3009601.06. 14:36
r3s5i5861 x 113326529.05. 02:16
r3s5sppc2 x 11,20040002.06. 02:31
r3s6x86_​641 x 11,6603,33302.06. 02:32
r3s6sx86_​642 x 22,66721,33202.06. 02:33
r3s7i6861 x 15331,06602.06. 02:34
r3s8i6866 x 13,20038,52602.06. 02:35
r4s0x86_​642 x 22,30018,39602.06. 02:37
r4s1arm​v7l4 x 11,5001,08001.06. 14:51
r4s1sarm​v7l4 x 11,5001,08002.06. 02:39
r4s2arm​v7l1 x 180079601.06. 14:56
r4s2sarm​v7l1 x 180053001.06. 14:58
r4s3i5861 x 150099602.06. 02:41
r4s3si6861 x 11,4662,93202.06. 02:43
r4s4ppc4 x 11,20049802.06. 02:45
r4s5arm​v7l1 x 1500002.06. 02:49
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25602.06. 02:51
r4s6sarm​v7l0 x 1 x 11,0006602.06. 02:55
r4s7i6864 x 11,83314,66402.06. 02:57
r4s7sx86_​642 x 11,8337,33202.06. 02:59
r4s8arm​v7l1 x 140039801.06. 15:18
r4s8sarm​v7l1 x 140039802.06. 03:00
r5s0x86_​642 x 22,20017,58230.05. 03:22
r5s1x86_​646 x 13,33340,09202.06. 03:03
r5s2x86_​644 x 12,70021,69902.06. 03:05
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87202.06. 03:06
r5s3sx86_​644 x 11,60012,74802.06. 03:08
r5s4x86_​642 x 22,53020,26402.06. 03:10
r5s4sx86_​642 x 22,53020,26402.06. 03:12
r5s5arm​v7l1 x 160059701.06. 03:28
r5s5sarm​v7l1 x 160060002.06. 03:16
r5s6ppc1 x 153313302.06. 03:23
r5s7arm​v7l1 x 15286402.06. 03:24
r5s7sarm​v7l1 x 15286402.06. 03:26
r6s0x86_​642 x 10 x 21,700136,18002.06. 03:29
r6s1x86_​642 x 12,0007,97802.06. 03:31
r6s2x86_​642 x 11,6679,57802.06. 03:32
r6s3x86_​644 x 22,20035,12001.06. 15:50
r6s4x86_​642 x 11,1004,37602.06. 03:34
r6s5i6861 x 11,5002,99202.06. 03:35
r6s6i6861 x 11,6003,19102.06. 03:38
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35602.06. 03:40
r7s0x86_​642 x 22,30018,40002.06. 03:41
r7s1x86_​644 x 11,60012,84002.06. 03:43
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700502.06. 03:44
r7s3sarm​v7l4 x 11,40035602.06. 03:47
r7s4arm​v7l1 x 153634802.06. 03:51
r7s4sarm​v7l4 x 11,5001,08002.06. 03:52
r7s5i6861 x 11,3002,59302.06. 03:54
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76702.06. 03:56
r7s7sx86_​642 x 22,30018,39602.06. 03:57
r7s8arm​v7l1 x 11,00099502.06. 04:00
r7s8sarm​v7l1 x 11,00099602.06. 04:01
r8s0x86_​642 x 22,30018,40002.06. 04:02
r8s1i5861 x 135070102.06. 04:04
r8s2x86_​642 x 22,10016,76002.06. 04:06
r8s2sx86_​642 x 22,10016,76002.06. 04:08
r8s3x86_​644 x 12,66721,28002.06. 04:10
r8s4x86_​644 x 21,60028,80002.06. 04:12
r8s4sx86_​644 x 21,60028,80002.06. 04:14
r8s5i6864 x 23,40054,40002.06. 04:15
r8s6arm​v7l1 x 150049802.06. 04:17
r8s7x86_​642 x 12,70010,77602.06. 04:18
r8s7sx86_​642 x 13,30013,19802.06. 04:19
r8s8x86_​642 x 11,3005,14402.06. 04:22
r9s0x86_​642 x 22,30018,39602.06. 04:23
r9s1x86_​642 x 12,0003,99202.06. 04:26
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74802.06. 04:27
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74802.06. 04:28
r9s3sx86_​644 x 13,00024,00002.06. 04:30
r9s4i6861 x 21,0003,99002.06. 04:31
r9s4sx86_​642 x 11,3335,34702.06. 04:37
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99802.06. 04:40
r9s6x86_​642 x 23,00023,94402.06. 04:41
r9s7arm​v7l2 x 11,000002.06. 04:45
r9s8sarm​v7l1 x 180079602.06. 04:46
ras0x86_​642 x 22,30018,41602.06. 04:47
ras1i6861 x 11,4002,79902.06. 04:50
ras2x86_​642 x 11,0674,26602.06. 04:50
ras3aarch​648 x 12,0004,00002.06. 04:51
ras3sarm​v7l1 x 11,30084002.06. 04:52
ras4arm​v7l1 x 150039802.06. 04:53
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002402.06. 04:55
ras5sarm​v7l2 x 11,0002401.06. 17:11
ras6aarch​648 x 12,0003,20020.05. 17:01
ras6sarm​v7l1 x 11,0001,98702.06. 04:56
ras7ppc1 x 13966502.06. 04:58
ras8x86_​644 x 11,60014,40002.06. 04:59
ras8sx86_​644 x 11,60012,74802.06. 05:01
rbs0i6862 x 22,50017,60002.06. 05:03
rbs1x86_​644 x 12,00015,97202.06. 05:04
rbs2x86_​644 x 12,00015,97202.06. 05:06
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962802.06. 05:07
rbs3sarm​v7l4 x 11,40035602.06. 05:08
rbs4x86_​644 x 11,2009,60002.06. 05:11
rbs4sx86_​644 x 11,60012,74802.06. 05:14
rbs5i6864 x 2049,53902.06. 05:15
rbs5saarch​644 x 11,6006402.06. 05:16
rbs6x86_​644 x 11,91515,32402.06. 05:17
rbs6sx86_​642 x 11,3335,33202.06. 05:20
rbs7arm​v7l4 x 19962801.06. 05:46
rbs7sarm​v7l4 x 19962402.06. 05:22
rbs8arm​v7l2 x 16662,65002.06. 05:24
rbs8sx86_​644 x 22,40038,70402.06. 05:26
rcs0x86_​648 x 22,40076,60002.06. 05:32
rcs1x86_​646 x 23,46783,37602.06. 05:33
rcs2x86_​642 x 12,80011,23202.06. 05:36
rcs3i6862 x 11,4005,58631.05. 05:56
rcs3sx86_​644 x 23,30052,69602.06. 05:37
rcs4x86_​642 x 11,1004,37602.06. 05:41
rcs4sx86_​644 x 11,1008,75202.06. 05:43
rcs5x86_​642 x 12,80011,19802.06. 05:44
rcs5sx86_​642 x 12,80011,19802.06. 05:48
rcs6x86_​644 x 23,50063,99202.06. 05:50
rcs7x86_​642 x 21,80014,39602.06. 05:52
rcs7sx86_​644 x 11,50011,98002.06. 05:55
rcs8x86_​6416 x 23,700217,15202.06. 06:01
rcs8sx86_​644 x 23,30052,79202.06. 06:03
rds0x86_​644 x 21,80031,99202.06. 06:05
rds1x86_​644 x 11,91015,32402.06. 06:06
rds2x86_​644 x 11,91015,32402.06. 06:08
rds3x86_​644 x 11,91015,32402.06. 06:10
rds4x86_​644 x 11,91015,32402.06. 06:11
rds5x86_​644 x 11,60012,74802.06. 06:13
rds6x86_​644 x 11,60012,74802.06. 06:14
rds7x86_​644 x 11,60012,74802.06. 06:16
rds8x86_​644 x 11,60012,74802.06. 06:17
res0x86_​644 x 21,80031,99202.06. 06:19
res1x86_​644 x 11,60014,40002.06. 06:20
res1sx86_​644 x 11,60014,40002.06. 06:21
res2x86_​644 x 11,60014,40002.06. 06:22
res3x86_​644 x 12,00015,97202.06. 06:24
res3saarch​640 x 1 x 11,0001,60002.06. 06:26
res4x86_​644 x 11,90015,05202.06. 06:27
res4sx86_​644 x 11,90015,05202.06. 06:29
res5x86_​642 x 22,20019,20002.06. 06:30
res5sx86_​642 x 22,20019,20002.06. 06:32
res6x86_​644 x 11,1008,75202.06. 06:34
res6saarch​644 x 101,60002.06. 06:35
res7arm​v7l0 x 1 x 11,0001202.06. 06:37
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05202.06. 06:39
res8sx86_​644 x 11,90015,05202.06. 06:40
rfs0x86_​6416 x 22,000128,00002.06. 06:42
rfs1aarch​644 x 11,50043202.06. 06:43
rfs2aarch​644 x 11,50043202.06. 06:44
rfs4arm​v7l1 x 180080002.06. 06:45
rfs4sarm​v7l1 x 180080002.06. 06:53
rfs6arm​v7l1 x 16671,33201.06. 19:10
rfs6sarm​v7l1 x 16671,33202.06. 07:01
 

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