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2024-05-17 - 10:49

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00017.05. 01:10
r0s1x86_​644 x 22,30055,99217.05. 01:11
r0s1sx86_​644 x 23,30052,67217.05. 01:12
r0s2x86_​644 x 23,50055,86417.05. 01:14
r0s2sx86_​6410 x 13,70073,99017.05. 01:16
r0s3x86_​648 x 23,600115,20017.05. 01:17
r0s3sx86_​644 x 23,60067,20017.05. 01:22
r0s4x86_​648 x 23,600115,20017.05. 01:24
r0s4sx86_​648 x 23,600115,20017.05. 01:25
r0s5x86_​648 x 23,500115,20017.05. 01:27
r0s5sx86_​648 x 23,600115,20017.05. 01:29
r0s6x86_​648 x 23,600115,20017.05. 01:34
r0s6sx86_​6410 x 23,700147,98017.05. 01:36
r0s7x86_​648 x 23,600115,20017.05. 01:40
r0s7sx86_​642 x 23,70029,52817.05. 01:45
r0s8x86_​648 x 23,600115,20017.05. 01:47
r0s8sx86_​646 x 23,47083,38817.05. 01:49
r1s0x86_​644 x 13,10024,79617.05. 01:51
r1s1x86_​642 x 22,60021,69617.05. 01:52
r1s2x86_​644 x 12,30028,00017.05. 01:54
r1s2sx86_​644 x 12,30028,00017.05. 01:56
r1s3x86_​644 x 12,80022,42417.05. 01:58
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004817.05. 02:00
r1s4sarm​v7l2 x 14004817.05. 02:01
r1s5aarch​644 x 11,20079617.05. 02:02
r1s6x86_​642 x 22,13017,06417.05. 02:02
r1s6sx86_​642 x 21,66713,33217.05. 02:04
r1s7arm​v6l1 x 11,66753017.05. 02:06
r1s8i6861 x 21,6006,39817.05. 02:06
r1s8sx86_​644 x 11,90015,19617.05. 02:08
r2s0x86_​644 x 13,10024,80017.05. 02:09
r2s1arm​v5tejl1 x 120019917.05. 02:11
r2s2arm​v7l1 x 172049917.05. 02:12
r2s3arm​v7l0 x 1 x 162462417.05. 02:12
r2s3sarm​v7l0 x 1 x 16001,20017.05. 02:14
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99917.05. 02:15
r2s6saarch​644 x 11,3506417.05. 02:17
r2s7aarch​644 x 12,40043217.05. 02:18
r2s7saarch​644 x 11,50043217.05. 02:20
r2s8ppc1 x 14006617.05. 02:22
r3s0i6864 x 23,50055,99217.05. 02:23
r3s1i6864 x 12,40019,12717.05. 02:25
r3s2riscv641 x 11,00028417.05. 02:26
r3s2sriscv644 x 1028417.05. 02:28
r3s3x86_​646 x 23,33379,99217.05. 02:29
r3s4aarch​646 x 11,3009617.05. 02:30
r3s5i5861 x 113326516.05. 14:38
r3s5sppc2 x 11,20040017.05. 02:35
r3s6x86_​641 x 11,6603,33317.05. 02:36
r3s6sx86_​642 x 22,66721,33217.05. 02:38
r3s7i6861 x 15331,06617.05. 02:40
r3s8i6866 x 13,20038,52616.05. 14:47
r4s0x86_​642 x 22,30018,39617.05. 02:41
r4s1arm​v7l4 x 11,5001,08017.05. 02:43
r4s1sarm​v7l4 x 11,5001,08017.05. 02:45
r4s2arm​v7l1 x 180079617.05. 02:47
r4s2sarm​v7l1 x 180053017.05. 02:49
r4s3i5861 x 150099617.05. 02:54
r4s3si6861 x 11,4662,93217.05. 02:56
r4s4ppc4 x 11,20049817.05. 02:58
r4s5arm​v7l1 x 1500017.05. 03:02
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25617.05. 03:03
r4s6sarm​v7l0 x 1 x 11,0006617.05. 03:07
r4s7i6864 x 11,83314,66416.05. 15:17
r4s7sx86_​642 x 11,8337,33217.05. 03:10
r4s8arm​v7l1 x 140039817.05. 03:12
r4s8sarm​v7l1 x 140039817.05. 03:13
r5s0x86_​642 x 22,20017,58217.05. 03:14
r5s1x86_​646 x 13,33340,09217.05. 03:15
r5s2x86_​644 x 12,70021,69917.05. 03:17
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87217.05. 03:19
r5s3sx86_​644 x 11,60012,74817.05. 03:21
r5s4x86_​642 x 22,53020,26417.05. 03:23
r5s4sx86_​642 x 22,53020,26417.05. 03:25
r5s5arm​v7l1 x 160059717.05. 03:28
r5s5sarm​v7l1 x 160060017.05. 03:31
r5s6ppc1 x 153313317.05. 03:37
r5s7arm​v7l1 x 15284817.05. 03:38
r5s7sarm​v7l1 x 15284817.05. 03:41
r6s0x86_​642 x 10 x 21,700136,18017.05. 03:43
r6s1x86_​642 x 12,0007,97817.05. 03:45
r6s2x86_​642 x 11,6679,57817.05. 03:47
r6s3x86_​644 x 22,20035,12017.05. 03:49
r6s4x86_​642 x 11,1004,37617.05. 03:51
r6s5i6861 x 11,5002,99217.05. 03:54
r6s6i6861 x 11,6003,19117.05. 03:56
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35617.05. 03:58
r7s0x86_​642 x 22,30018,40016.05. 16:08
r7s1x86_​644 x 11,60012,84017.05. 04:00
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700517.05. 04:02
r7s3sarm​v7l4 x 11,40035617.05. 04:06
r7s4arm​v7l1 x 153634817.05. 04:09
r7s4sarm​v7l4 x 11,5001,08017.05. 04:11
r7s5i6861 x 11,3002,59317.05. 04:12
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76717.05. 04:13
r7s7sx86_​642 x 22,30018,39617.05. 04:15
r7s8arm​v7l1 x 11,00099517.05. 04:17
r7s8sarm​v7l1 x 11,00079617.05. 04:19
r8s0x86_​642 x 22,30018,40017.05. 04:20
r8s1i5861 x 135070117.05. 04:21
r8s2x86_​642 x 22,10016,76017.05. 04:22
r8s2sx86_​642 x 22,10016,76017.05. 04:24
r8s3x86_​644 x 12,66721,28017.05. 04:26
r8s4x86_​644 x 21,60028,80017.05. 04:27
r8s4sx86_​644 x 21,60028,80017.05. 04:29
r8s5i6864 x 23,40054,40017.05. 04:31
r8s6arm​v7l1 x 150049817.05. 04:32
r8s7x86_​642 x 12,70010,77617.05. 04:33
r8s7sx86_​642 x 13,30013,19817.05. 04:35
r8s8x86_​642 x 11,3005,14417.05. 04:38
r9s0x86_​642 x 22,30018,40017.05. 04:40
r9s1x86_​642 x 12,0003,99217.05. 04:41
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74817.05. 04:43
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74817.05. 04:45
r9s3sx86_​644 x 13,00024,00017.05. 04:46
r9s4i6861 x 21,0003,99017.05. 04:48
r9s4sx86_​642 x 11,3335,34717.05. 04:54
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99817.05. 04:57
r9s6x86_​642 x 23,00023,94417.05. 04:58
r9s7arm​v7l2 x 11,000017.05. 05:00
r9s8sarm​v7l1 x 180079617.05. 05:01
ras0x86_​642 x 22,30018,41617.05. 05:03
ras1i6861 x 11,4002,79917.05. 05:05
ras2x86_​642 x 11,0674,26617.05. 05:05
ras3aarch​648 x 12,0004,00017.05. 05:06
ras3sarm​v7l1 x 11,30084017.05. 05:07
ras4arm​v7l1 x 150039817.05. 05:08
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002417.05. 05:09
ras5sarm​v7l2 x 11,0002417.05. 05:10
ras6aarch​648 x 12,0003,20017.05. 05:11
ras6sarm​v7l1 x 11,0001,98717.05. 05:12
ras7ppc1 x 13966517.05. 05:13
ras8x86_​644 x 11,60014,40017.05. 05:14
ras8sx86_​644 x 11,60012,74817.05. 05:15
rbs0i6862 x 22,50017,60017.05. 05:17
rbs1x86_​644 x 12,00015,97217.05. 05:18
rbs2x86_​644 x 12,00015,97217.05. 05:19
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962817.05. 05:21
rbs3sarm​v7l4 x 11,40035617.05. 05:22
rbs4x86_​644 x 11,2009,60017.05. 05:25
rbs4sx86_​644 x 11,60012,74817.05. 05:25
rbs5i6864 x 2049,53917.05. 05:27
rbs5saarch​644 x 11,6006417.05. 05:28
rbs6x86_​644 x 11,91515,32417.05. 05:29
rbs6sx86_​642 x 11,3335,33217.05. 05:31
rbs7arm​v7l4 x 19962817.05. 05:33
rbs7sarm​v7l4 x 19962417.05. 05:34
rbs8arm​v7l2 x 16662,65017.05. 05:36
rbs8sx86_​644 x 22,40038,70417.05. 05:38
rcs0x86_​648 x 22,40076,60017.05. 05:42
rcs1x86_​646 x 23,46783,37617.05. 05:44
rcs2x86_​642 x 12,80011,23217.05. 05:46
rcs3i6862 x 11,4005,58617.05. 05:47
rcs3sx86_​644 x 23,30052,69617.05. 05:48
rcs4x86_​642 x 11,1004,37617.05. 05:51
rcs4sx86_​644 x 11,1008,75217.05. 05:54
rcs5x86_​642 x 12,80011,19817.05. 05:55
rcs5sx86_​642 x 12,80011,19817.05. 05:58
rcs6x86_​644 x 23,50063,99211.05. 17:51
rcs7x86_​642 x 21,80014,39617.05. 06:00
rcs7sx86_​644 x 11,50011,98017.05. 06:02
rcs8x86_​6416 x 23,700217,15217.05. 06:08
rcs8sx86_​644 x 23,30052,79217.05. 06:10
rds0x86_​644 x 21,80031,99216.05. 18:20
rds1x86_​644 x 11,91015,32417.05. 06:14
rds2x86_​644 x 11,91015,32417.05. 06:15
rds3x86_​644 x 11,91015,32417.05. 06:16
rds4x86_​644 x 11,91015,32417.05. 06:18
rds5x86_​644 x 11,60012,74817.05. 06:19
rds6x86_​644 x 11,60012,74817.05. 06:21
rds7x86_​644 x 11,60012,74817.05. 06:22
rds8x86_​644 x 11,60012,74817.05. 06:23
res0x86_​644 x 21,80031,99217.05. 06:25
res1x86_​644 x 11,60014,40017.05. 06:27
res1sx86_​644 x 11,60014,40017.05. 06:28
res2x86_​644 x 11,60014,40017.05. 06:29
res3x86_​644 x 12,00015,97217.05. 06:30
res3saarch​640 x 1 x 11,0001,60017.05. 06:32
res4x86_​644 x 11,90015,05217.05. 06:33
res4sx86_​644 x 11,90015,05217.05. 06:34
res5x86_​642 x 22,20019,20017.05. 06:35
res5sx86_​642 x 22,20019,20017.05. 06:37
res6x86_​644 x 11,1008,75217.05. 06:38
res6saarch​644 x 101,60017.05. 06:40
res7arm​v7l0 x 1 x 11,0001217.05. 06:41
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05217.05. 06:43
res8sx86_​644 x 11,90015,05217.05. 06:44
rfs0x86_​6416 x 22,000128,00017.05. 06:46
rfs1aarch​644 x 11,50043217.05. 06:47
rfs2aarch​644 x 11,50043217.05. 06:48
rfs4arm​v7l1 x 180080017.05. 06:49
rfs4sarm​v7l1 x 180080017.05. 06:55
 

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