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2025-12-10 - 16:09

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00010.12. 13:10
r0s0sx86_​644 x 23,40054,39210.12. 13:10
r0s1x86_​644 x 22,30055,99210.12. 13:11
r0s1sx86_​644 x 23,30052,79210.12. 13:11
r0s2x86_​644 x 23,50055,86410.12. 13:12
r0s2sx86_​6410 x 13,70073,99010.12. 13:12
r0s3x86_​648 x 23,600115,20010.12. 13:13
r0s3sx86_​644 x 23,60067,20010.12. 13:15
r0s4x86_​648 x 23,600115,20010.12. 13:16
r0s4sx86_​648 x 23,600115,20010.12. 13:16
r0s5x86_​648 x 23,500115,20010.12. 13:17
r0s5sx86_​648 x 23,600115,20010.12. 13:18
r0s6x86_​648 x 23,600115,20010.12. 13:19
r0s6sx86_​6410 x 23,700147,98010.12. 13:20
r0s7x86_​648 x 23,600115,20010.12. 13:21
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20010.12. 13:22
r0s8sx86_​646 x 23,47083,37610.12. 13:23
r1s0x86_​644 x 13,10024,80010.12. 13:23
r1s1x86_​642 x 22,60021,69610.12. 13:24
r1s2x86_​644 x 12,30028,00010.12. 13:25
r1s2sx86_​644 x 12,30028,00010.12. 13:25
r1s3x86_​644 x 12,80022,42410.12. 13:26
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004810.12. 13:27
r1s4sarm​v7l2 x 14004810.12. 13:27
r1s5aarch​644 x 11,20079610.12. 13:28
r1s6x86_​642 x 22,13017,06410.12. 13:28
r1s6sx86_​642 x 21,66713,33210.12. 13:29
r1s7arm​v6l1 x 11,66753010.12. 13:29
r1s8i6861 x 21,6006,39810.12. 13:30
r1s8sx86_​644 x 11,90015,19610.12. 13:31
r2s0x86_​644 x 13,10024,80010.12. 13:31
r2s1arm​v5tejl1 x 120019910.12. 13:32
r2s2arm​v7l1 x 172049910.12. 13:32
r2s3arm​v7l0 x 1 x 162462410.12. 13:32
r2s3sarm​v7l0 x 2 x 16001,20010.12. 13:33
r2s4mips​641 x 180053129.09. 13:34
r2s5ppc1 x 13966611.11. 13:35
r2s5sarm​v7l4 x 11,20015210.12. 13:34
r2s6i6861 x 11,5002,99910.12. 13:35
r2s6saarch​644 x 11,3506410.12. 13:36
r2s7aarch​644 x 12,40043210.12. 13:36
r2s7saarch​644 x 11,50043210.12. 13:37
r2s8ppc1 x 14006610.12. 13:37
r3s0i6864 x 23,50055,99210.12. 13:38
r3s1i6864 x 12,40019,12710.12. 13:39
r3s2riscv641 x 11,00028410.12. 13:39
r3s2sriscv644 x 1028410.12. 13:41
r3s3x86_​646 x 23,33379,99210.12. 13:41
r3s3sx86_​644 x 13,40011,98010.12. 13:42
r3s4aarch​646 x 11,3009610.12. 13:43
r3s5i5861 x 113326510.12. 13:44
r3s5sppc2 x 11,20040010.12. 13:46
r3s6x86_​641 x 21,6606,66610.12. 13:47
r3s6sx86_​642 x 22,66721,33210.12. 13:47
r3s7i6861 x 15331,06610.12. 13:48
r3s8i6864 x 13,20027,36910.12. 13:49
r4s0x86_​642 x 22,30018,40010.12. 13:50
r4s1arm​v7l4 x 11,50072010.12. 13:51
r4s1sarm​v7l4 x 11,50086410.12. 13:51
r4s2arm​v7l1 x 180079610.12. 13:52
r4s2sarm​v7l1 x 180053010.12. 13:53
r4s3i5861 x 150099610.12. 13:55
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049810.12. 13:56
r4s5arm​v7l1 x 1500010.12. 14:00
r4s5saarch​644 x 11,60020010.12. 14:01
r4s6x86_​644 x 23,40054,25610.12. 14:01
r4s6sarm​v7l0 x 1 x 11,0006610.12. 14:02
r4s7i6864 x 11,83314,66410.12. 14:03
r4s7sx86_​642 x 11,8337,33210.12. 14:04
r4s8arm​v7l1 x 140039810.12. 14:04
r4s8sarm​v7l1 x 140039810.12. 14:05
r5s0x86_​642 x 22,20017,58210.12. 14:06
r5s1x86_​646 x 13,33340,08610.12. 14:06
r5s2x86_​644 x 12,70021,69910.12. 14:06
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87210.12. 14:07
r5s3sx86_​644 x 11,60012,74810.12. 14:08
r5s4x86_​642 x 22,53020,26410.12. 14:09
r5s4sx86_​644 x 11,60012,74810.12. 14:09
r5s5arm​v7l1 x 160059710.12. 14:11
r5s5sarm​v7l1 x 160060010.12. 14:13
r5s6ppc1 x 153313310.12. 14:17
r5s7arm​v7l1 x 15286410.12. 14:17
r5s7sarm​v7l1 x 15284810.12. 14:19
r5s8x86_​644 x 12,00015,97210.12. 14:20
r6s0x86_​642 x 10 x 21,700136,18010.12. 14:21
r6s1x86_​642 x 12,0007,97810.12. 14:21
r6s2x86_​642 x 11,6679,57810.12. 14:22
r6s3x86_​644 x 22,20035,12010.12. 14:22
r6s4x86_​642 x 11,1004,37610.12. 14:23
r6s5i6861 x 11,5002,99210.12. 14:24
r6s6i6861 x 11,6003,19210.12. 14:25
r6s7i6862 x 12,3009,17610.12. 14:25
r6s8x86_​642 x 22,30018,35610.12. 14:26
r7s0x86_​642 x 22,30018,40010.12. 14:27
r7s1x86_​644 x 11,60012,83910.12. 14:27
r7s2aarch​642 x 11,7009610.12. 14:27
r7s2sriscv644 x 1028410.12. 14:28
r7s3arm​v6l1 x 1700510.12. 14:30
r7s3sarm​v7l4 x 11,40035610.12. 14:32
r7s4arm​v7l1 x 153634810.12. 14:33
r7s4sarm​v7l4 x 11,5001,08010.12. 14:34
r7s5i6861 x 11,3002,59310.12. 14:34
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76710.12. 02:32
r7s7sx86_​642 x 22,30018,39610.12. 02:32
r7s8arm​v7l1 x 11,00099510.12. 02:33
r7s8sarm​v7l1 x 11,00079610.12. 02:33
r8s0x86_​642 x 22,30018,40010.12. 02:34
r8s1i5861 x 135070110.12. 02:35
r8s3x86_​644 x 12,66721,28010.12. 02:36
r8s4x86_​644 x 21,60028,80010.12. 02:37
r8s4sx86_​644 x 21,60028,80010.12. 02:37
r8s5i6864 x 23,40054,40010.12. 02:38
r8s6arm​v7l1 x 150049810.12. 02:39
r8s6sx86_​644 x 13,30026,41610.12. 02:39
r8s7x86_​644 x 13,20025,49610.12. 02:40
r8s7sx86_​642 x 13,00011,98010.12. 02:40
r8s8x86_​642 x 11,3005,14410.12. 02:41
r9s0x86_​644 x 23,60057,60010.12. 02:42
r9s1x86_​642 x 12,0003,99210.12. 02:42
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74810.12. 02:43
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74810.12. 02:44
r9s3sx86_​644 x 13,00024,00010.12. 02:45
r9s4i6861 x 21,0003,99010.12. 02:45
r9s4sx86_​642 x 11,3335,34710.12. 02:46
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19810.12. 02:47
r9s6x86_​642 x 23,00023,94410.12. 02:47
r9s7arm​v7l2 x 11,000010.12. 02:48
r9s8sarm​v7l1 x 180079610.12. 02:49
ras0x86_​642 x 22,30018,41810.12. 02:50
ras1i6861 x 11,4002,79910.12. 02:50
ras2x86_​642 x 11,0674,26610.12. 02:51
ras2sx86_​644 x 11,90015,05210.12. 02:51
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084010.12. 02:52
ras4aarch​648 x 12,40038410.12. 02:52
ras4saarch​648 x 12,40038429.09. 03:02
ras5arm​v7l2 x 11,0002410.12. 02:53
ras5sarm​v7l2 x 11,0002410.12. 02:53
ras6aarch​648 x 12,0003,20010.12. 02:54
ras6sarm​v7l1 x 11,0001,98710.12. 02:54
ras7ppc1 x 13966510.12. 02:55
ras8x86_​644 x 11,60014,40010.12. 02:56
ras8sx86_​644 x 11,60012,74810.12. 02:56
rbs0i6862 x 22,50017,60010.12. 02:57
rbs1x86_​644 x 12,00015,97210.12. 02:57
rbs2x86_​644 x 12,00015,97210.12. 02:58
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962410.12. 02:59
rbs3sarm​v7l4 x 11,40035610.12. 02:59
rbs4x86_​644 x 11,2009,60010.12. 03:00
rbs4sx86_​644 x 11,60012,74810.12. 03:01
rbs5i6864 x 2049,41510.12. 03:01
rbs5saarch​644 x 11,6006410.12. 03:02
rbs6x86_​644 x 11,91515,32410.12. 03:02
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961210.12. 03:03
rbs7sarm​v7l4 x 19962410.12. 03:05
rbs8arm​v7l2 x 16662,65010.12. 03:06
rbs8sx86_​644 x 22,40038,70410.12. 03:07
rcs0x86_​648 x 22,40076,60810.12. 03:08
rcs1x86_​646 x 23,46783,37610.12. 03:09
rcs2x86_​642 x 12,80011,23210.12. 03:10
rcs3i6862 x 11,4005,58810.12. 03:10
rcs3sx86_​644 x 13,30026,39610.12. 03:11
rcs4x86_​642 x 11,1004,37610.12. 03:12
rcs5x86_​642 x 12,80011,19810.12. 03:13
rcs5sx86_​642 x 12,80011,19810.12. 03:15
rcs6x86_​644 x 23,50063,99210.12. 03:16
rcs7x86_​642 x 21,80014,39610.12. 03:17
rcs7sx86_​644 x 11,50011,98010.12. 03:18
rcs8x86_​6416 x 23,700217,15210.12. 03:22
rcs8sx86_​644 x 23,30052,80010.12. 03:22
rds0x86_​644 x 21,80031,99210.12. 03:23
rds1x86_​644 x 11,60012,74810.12. 03:24
rds2x86_​644 x 11,60012,74810.12. 03:24
rds3x86_​644 x 11,60012,74810.12. 03:25
rds4x86_​644 x 11,60012,74810.12. 03:26
rds5x86_​644 x 11,60012,74810.12. 03:26
rds6x86_​644 x 11,60012,74810.12. 03:26
rds7x86_​644 x 11,60012,74810.12. 03:27
rds8x86_​644 x 11,60012,74810.12. 03:27
res0x86_​644 x 23,40054,39210.12. 03:28
res1x86_​644 x 11,60014,40010.12. 03:29
res1sx86_​644 x 11,60014,40010.12. 03:30
res2x86_​644 x 11,60014,40010.12. 03:30
res3x86_​644 x 12,00015,97210.12. 03:31
res3saarch​640 x 1 x 11,0001,60010.12. 03:31
res4x86_​644 x 11,90015,05210.12. 03:32
res4sx86_​644 x 11,90015,05210.12. 03:32
res5x86_​642 x 22,20019,20010.12. 03:33
res5sx86_​642 x 22,20019,20010.12. 03:33
res6x86_​644 x 11,1008,75210.12. 03:34
res6saarch​644 x 101,60010.12. 03:35
res7arm​v7l0 x 1 x 11,0001210.12. 03:36
res7sarm​v7l0 x 1 x 11,0001210.12. 03:37
res8x86_​644 x 11,90015,05210.12. 03:37
res8sx86_​644 x 11,90015,05210.12. 03:38
rfs0x86_​6416 x 22,000127,96810.12. 03:38
rfs1aarch​644 x 11,50043210.12. 03:39
rfs1saarch​644 x 11,50043210.12. 03:39
rfs2x86_​644 x 13,00023,99610.12. 03:40
rfs2sx86_​642 x 13,00011,99810.12. 03:40
rfs3x86_​644 x 11,60012,74810.12. 03:40
rfs3sx86_​644 x 11,60012,74810.12. 03:41
rfs4aarch​641 x 11,4001,60010.12. 10:26
rfs4sarm​v7l1 x 180080010.12. 10:27
rfs5aarch​644 x 11,2006410.12. 03:44
rfs5saarch​644 x 11,2006427.08. 03:49
rfs6arm​v7l1 x 16671,33210.12. 03:44
rfs6sarm​v7l1 x 16671,33210.12. 03:45
rfs7x86_​644 x 22,60041,60010.12. 03:46
rfs7sx86_​644 x 17006,44810.12. 03:46
rfs8arm​v7l1 x 11,00012004.03. 03:47
 

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