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2024-05-15 - 02:01

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00015.05. 01:10
r0s1x86_​644 x 22,30055,99214.05. 13:12
r0s1sx86_​644 x 23,30052,67215.05. 01:12
r0s2x86_​644 x 23,50055,86415.05. 01:13
r0s2sx86_​6410 x 13,70073,99015.05. 01:15
r0s3x86_​648 x 23,600115,20015.05. 01:16
r0s3sx86_​644 x 23,60067,20015.05. 01:21
r0s4x86_​648 x 23,600115,20015.05. 01:23
r0s4sx86_​648 x 23,600115,20015.05. 01:24
r0s5x86_​648 x 23,500115,20015.05. 01:26
r0s5sx86_​648 x 23,600115,20015.05. 01:28
r0s6x86_​648 x 23,600115,20015.05. 01:32
r0s6sx86_​6410 x 23,700147,98015.05. 01:34
r0s7x86_​648 x 23,600115,20015.05. 01:36
r0s7sx86_​642 x 23,70029,52815.05. 01:41
r0s8x86_​648 x 23,600115,20015.05. 01:43
r0s8sx86_​646 x 23,47083,38815.05. 01:45
r1s0x86_​644 x 13,10024,79615.05. 01:46
r1s1x86_​642 x 22,60021,69615.05. 01:48
r1s2x86_​644 x 12,30028,00015.05. 01:49
r1s2sx86_​644 x 12,30028,00015.05. 01:50
r1s3x86_​644 x 12,80022,42415.05. 01:51
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004815.05. 01:53
r1s4sarm​v7l2 x 14004815.05. 01:54
r1s5aarch​644 x 11,20079615.05. 01:55
r1s6x86_​642 x 22,13017,06415.05. 01:56
r1s6sx86_​642 x 21,66713,33215.05. 01:57
r1s7arm​v6l1 x 11,66753015.05. 01:59
r1s8i6861 x 21,6006,39815.05. 02:00
r1s8sx86_​644 x 11,90015,19614.05. 14:09
r2s0x86_​644 x 13,10024,80014.05. 14:10
r2s1arm​v5tejl1 x 120019914.05. 14:12
r2s2arm​v7l1 x 172049914.05. 14:15
r2s3arm​v7l0 x 1 x 162462414.05. 14:16
r2s3sarm​v7l0 x 1 x 16001,20014.05. 14:17
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99914.05. 14:19
r2s6saarch​644 x 11,3506414.05. 14:20
r2s7aarch​644 x 12,40043214.05. 14:21
r2s7saarch​644 x 11,50043214.05. 14:24
r2s8ppc1 x 14006614.05. 14:25
r3s0i6864 x 23,50055,99214.05. 14:27
r3s1i6864 x 12,40019,12714.05. 14:29
r3s2riscv641 x 11,00028414.05. 14:30
r3s2sriscv644 x 1028414.05. 14:32
r3s3x86_​646 x 23,33379,99214.05. 14:33
r3s4aarch​646 x 11,3009614.05. 14:35
r3s5i5861 x 113326514.05. 14:40
r3s5sppc2 x 11,20040014.05. 14:43
r3s6x86_​641 x 11,6603,33314.05. 14:44
r3s6sx86_​642 x 22,66721,33214.05. 14:46
r3s7i6861 x 15331,06614.05. 14:47
r3s8i6866 x 13,20038,52614.05. 14:48
r4s0x86_​642 x 22,30018,39614.05. 14:50
r4s1arm​v7l4 x 11,5001,08014.05. 14:51
r4s1sarm​v7l4 x 11,5001,08014.05. 14:53
r4s2arm​v7l1 x 180079614.05. 14:57
r4s2sarm​v7l1 x 180053014.05. 14:59
r4s3i5861 x 150099614.05. 15:02
r4s3si6861 x 11,4662,93214.05. 15:04
r4s4ppc4 x 11,20049814.05. 15:06
r4s5arm​v7l1 x 1500014.05. 15:07
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25614.05. 15:08
r4s6sarm​v7l0 x 1 x 11,0006614.05. 15:11
r4s7i6864 x 11,83314,66414.05. 15:14
r4s7sx86_​642 x 11,8337,33214.05. 15:15
r4s8arm​v7l1 x 140039814.05. 15:17
r4s8sarm​v7l1 x 140039814.05. 15:18
r5s0x86_​642 x 22,20017,58214.05. 15:20
r5s1x86_​646 x 13,33340,09214.05. 15:20
r5s2x86_​644 x 12,70021,69914.05. 15:22
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87214.05. 15:24
r5s3sx86_​644 x 11,60012,74814.05. 15:26
r5s4x86_​642 x 22,53020,26414.05. 15:28
r5s4sx86_​642 x 22,53020,26414.05. 15:30
r5s5arm​v7l1 x 160059714.05. 15:33
r5s5sarm​v7l1 x 160060014.05. 15:36
r5s6ppc1 x 153313314.05. 15:42
r5s7arm​v7l1 x 15286414.05. 15:43
r5s7sarm​v7l1 x 15286414.05. 15:45
r6s0x86_​642 x 10 x 21,700136,18014.05. 15:48
r6s1x86_​642 x 12,0007,97814.05. 15:50
r6s2x86_​642 x 11,6679,57814.05. 15:52
r6s3x86_​644 x 22,20035,12014.05. 15:54
r6s4x86_​642 x 11,1004,37614.05. 15:56
r6s5i6861 x 11,5002,99214.05. 15:58
r6s6i6861 x 11,6003,19114.05. 16:00
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35614.05. 16:02
r7s0x86_​642 x 22,30018,40014.05. 16:04
r7s1x86_​644 x 11,60012,84014.05. 16:05
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700514.05. 16:07
r7s3sarm​v7l4 x 11,40015214.05. 16:09
r7s4arm​v7l1 x 153634814.05. 16:12
r7s4sarm​v7l4 x 11,5001,08014.05. 16:14
r7s5i6861 x 11,3002,59314.05. 16:15
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76714.05. 16:16
r7s7sx86_​642 x 22,30018,39614.05. 16:17
r7s8arm​v7l1 x 11,00099514.05. 16:19
r7s8sarm​v7l1 x 11,00099614.05. 16:21
r8s0x86_​642 x 22,30018,40014.05. 16:22
r8s1i5861 x 135070114.05. 16:24
r8s2x86_​642 x 22,10016,76014.05. 16:25
r8s2sx86_​642 x 22,10016,76014.05. 16:27
r8s3x86_​644 x 12,66721,28014.05. 16:29
r8s4x86_​644 x 21,60028,80014.05. 16:31
r8s4sx86_​644 x 21,60028,80014.05. 16:33
r8s5i6864 x 23,40054,40014.05. 16:35
r8s6arm​v7l1 x 150049814.05. 16:36
r8s7x86_​642 x 12,70010,77614.05. 16:37
r8s7sx86_​642 x 13,30013,19814.05. 16:38
r8s8x86_​642 x 11,3005,14414.05. 16:40
r9s0x86_​642 x 22,30018,40014.05. 16:42
r9s1x86_​642 x 12,0003,99214.05. 16:44
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74814.05. 16:46
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74814.05. 16:49
r9s3sx86_​644 x 13,00024,00014.05. 16:50
r9s4i6861 x 21,0003,99014.05. 16:52
r9s4sx86_​642 x 11,3335,34714.05. 16:58
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99814.05. 17:00
r9s6x86_​642 x 23,00023,94414.05. 04:57
r9s7arm​v7l2 x 11,000014.05. 17:02
r9s8sarm​v7l1 x 180079614.05. 17:03
ras0x86_​642 x 22,30018,41614.05. 17:05
ras1i6861 x 11,4002,79914.05. 17:06
ras2x86_​642 x 11,0674,26614.05. 17:07
ras3aarch​648 x 12,0004,00014.05. 17:08
ras3sarm​v7l1 x 11,30084014.05. 17:09
ras4arm​v7l1 x 150039814.05. 17:10
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002414.05. 17:11
ras5sarm​v7l2 x 11,0002414.05. 17:12
ras6aarch​648 x 12,0003,20014.05. 17:13
ras6sarm​v7l1 x 11,0001,98714.05. 17:16
ras7ppc1 x 13966514.05. 17:17
ras8x86_​644 x 11,60014,40014.05. 17:18
ras8sx86_​644 x 11,60012,74814.05. 17:19
rbs0i6862 x 22,50017,60014.05. 17:21
rbs1x86_​644 x 12,00015,97214.05. 17:22
rbs2x86_​644 x 12,00015,97214.05. 17:24
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962814.05. 17:25
rbs3sarm​v7l4 x 11,40035614.05. 17:26
rbs4x86_​644 x 11,2009,60014.05. 17:28
rbs4sx86_​644 x 11,60012,74814.05. 17:30
rbs5i6864 x 2049,53914.05. 17:31
rbs5saarch​644 x 11,6006414.05. 17:32
rbs6x86_​644 x 11,91515,32414.05. 17:33
rbs6sx86_​642 x 11,3335,33214.05. 17:35
rbs7arm​v7l4 x 19962814.05. 17:36
rbs7sarm​v7l4 x 19962414.05. 17:38
rbs8arm​v7l2 x 16662,65014.05. 17:40
rbs8sx86_​644 x 22,40038,70414.05. 17:43
rcs0x86_​648 x 22,40076,60014.05. 17:47
rcs1x86_​646 x 23,46783,37614.05. 17:49
rcs2x86_​642 x 12,80011,23214.05. 17:51
rcs3i6862 x 11,4005,58614.05. 17:52
rcs3sx86_​644 x 23,30052,69614.05. 17:54
rcs4x86_​642 x 11,1004,37614.05. 17:57
rcs4sx86_​644 x 11,1008,75214.05. 17:59
rcs5x86_​642 x 12,80011,19814.05. 18:01
rcs5sx86_​642 x 12,80011,19814.05. 06:01
rcs6x86_​644 x 23,50063,99211.05. 17:51
rcs7x86_​642 x 21,80014,39614.05. 18:04
rcs7sx86_​644 x 11,50011,98014.05. 18:06
rcs8x86_​6416 x 23,700217,15214.05. 18:12
rcs8sx86_​644 x 23,30052,79214.05. 18:14
rds0x86_​644 x 21,80031,99214.05. 18:16
rds1x86_​644 x 11,91015,32414.05. 18:17
rds2x86_​644 x 11,91015,32414.05. 18:18
rds3x86_​644 x 11,91015,32414.05. 18:20
rds4x86_​644 x 11,91015,32414.05. 18:21
rds5x86_​644 x 11,60012,74814.05. 18:22
rds6x86_​644 x 11,60012,74814.05. 18:24
rds7x86_​644 x 11,60012,74814.05. 18:26
rds8x86_​644 x 11,60012,74814.05. 18:27
res0x86_​644 x 21,80031,99214.05. 18:28
res1x86_​644 x 11,60014,40014.05. 18:30
res1sx86_​644 x 11,60014,40014.05. 18:31
res2x86_​644 x 11,60014,40014.05. 18:32
res3x86_​644 x 12,00015,97214.05. 18:34
res3saarch​640 x 1 x 11,0001,60014.05. 18:35
res4x86_​644 x 11,90015,05214.05. 18:37
res4sx86_​644 x 11,90015,05214.05. 18:38
res5x86_​642 x 22,20019,20014.05. 06:39
res5sx86_​642 x 22,20019,20014.05. 18:40
res6x86_​644 x 11,1008,75214.05. 18:42
res6saarch​644 x 101,60014.05. 18:44
res7arm​v7l0 x 1 x 11,0001214.05. 18:47
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05214.05. 18:49
res8sx86_​644 x 11,90015,05214.05. 18:50
rfs0x86_​6416 x 22,000128,00014.05. 18:52
rfs1aarch​644 x 11,50043214.05. 18:53
rfs2aarch​644 x 11,50043214.05. 18:54
rfs4arm​v7l1 x 180080014.05. 18:55
rfs4sarm​v7l1 x 180080014.05. 19:02
 

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