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2024-05-18 - 11:20

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00018.05. 01:10
r0s1x86_​644 x 22,30055,99218.05. 01:12
r0s1sx86_​644 x 23,30052,67218.05. 01:13
r0s2x86_​644 x 23,50055,86418.05. 01:15
r0s2sx86_​6410 x 13,70073,99018.05. 01:16
r0s3x86_​648 x 23,600115,20018.05. 01:18
r0s3sx86_​644 x 23,60067,20018.05. 01:23
r0s4x86_​648 x 23,600115,20018.05. 01:25
r0s4sx86_​648 x 23,600115,20018.05. 01:26
r0s5x86_​648 x 23,500115,20018.05. 01:28
r0s5sx86_​648 x 23,600115,20018.05. 01:30
r0s6x86_​648 x 23,600115,20017.05. 13:36
r0s6sx86_​6410 x 23,700147,98018.05. 01:35
r0s7x86_​648 x 23,600115,20018.05. 01:38
r0s7sx86_​642 x 23,70029,52818.05. 01:42
r0s8x86_​648 x 23,600115,20018.05. 01:44
r0s8sx86_​646 x 23,47083,38818.05. 01:46
r1s0x86_​644 x 13,10024,79618.05. 01:48
r1s1x86_​642 x 22,60021,69618.05. 01:50
r1s2x86_​644 x 12,30028,00018.05. 01:51
r1s2sx86_​644 x 12,30028,00018.05. 01:53
r1s3x86_​644 x 12,80022,42418.05. 01:55
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004818.05. 01:56
r1s4sarm​v7l2 x 14004818.05. 01:57
r1s5aarch​644 x 11,20079618.05. 01:58
r1s6x86_​642 x 22,13017,06418.05. 01:59
r1s6sx86_​642 x 21,66713,33218.05. 02:00
r1s7arm​v6l1 x 11,66753018.05. 02:02
r1s8i6861 x 21,6006,39818.05. 02:03
r1s8sx86_​644 x 11,90015,19618.05. 02:05
r2s0x86_​644 x 13,10024,80018.05. 02:06
r2s1arm​v5tejl1 x 120019918.05. 02:07
r2s2arm​v7l1 x 172049918.05. 02:08
r2s3arm​v7l0 x 1 x 162462418.05. 02:08
r2s3sarm​v7l0 x 1 x 16001,20018.05. 02:10
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99918.05. 02:11
r2s6saarch​644 x 11,3506418.05. 02:13
r2s7aarch​644 x 12,40043218.05. 02:14
r2s7saarch​644 x 11,50043218.05. 02:17
r2s8ppc1 x 14006618.05. 02:18
r3s0i6864 x 23,50055,99218.05. 02:20
r3s1i6864 x 12,40019,12718.05. 02:21
r3s2riscv641 x 11,00028418.05. 02:22
r3s2sriscv644 x 1028418.05. 02:24
r3s3x86_​646 x 23,33379,99218.05. 02:25
r3s4aarch​646 x 11,3009618.05. 02:27
r3s5i5861 x 113326518.05. 02:32
r3s5sppc2 x 11,20040018.05. 02:34
r3s6x86_​641 x 11,6603,33318.05. 02:35
r3s6sx86_​642 x 22,66721,33218.05. 02:36
r3s7i6861 x 15331,06618.05. 02:38
r3s8i6866 x 13,20038,52618.05. 02:39
r4s0x86_​642 x 22,30018,39618.05. 02:40
r4s1arm​v7l4 x 11,50079218.05. 02:41
r4s1sarm​v7l4 x 11,5001,08018.05. 02:44
r4s2arm​v7l1 x 180079618.05. 02:46
r4s2sarm​v7l1 x 180039818.05. 02:48
r4s3i5861 x 150099618.05. 02:52
r4s3si6861 x 11,4662,93218.05. 02:55
r4s4ppc4 x 11,20049818.05. 02:55
r4s5arm​v7l1 x 1500018.05. 03:00
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25618.05. 03:00
r4s6sarm​v7l0 x 1 x 11,0006618.05. 03:05
r4s7i6864 x 11,83314,66418.05. 03:08
r4s7sx86_​642 x 11,8337,33217.05. 15:19
r4s8arm​v7l1 x 140039818.05. 03:10
r4s8sarm​v7l1 x 140039817.05. 15:22
r5s0x86_​642 x 22,20017,58218.05. 03:11
r5s1x86_​646 x 13,33340,09218.05. 03:12
r5s2x86_​644 x 12,70021,69918.05. 03:14
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87218.05. 03:16
r5s3sx86_​644 x 11,60012,74818.05. 03:17
r5s4x86_​642 x 22,53020,26418.05. 03:19
r5s4sx86_​642 x 22,53020,26418.05. 03:21
r5s5arm​v7l1 x 160059718.05. 03:24
r5s5sarm​v7l1 x 160060018.05. 03:27
r5s6ppc1 x 153313318.05. 03:33
r5s7arm​v7l1 x 15286418.05. 03:34
r5s7sarm​v7l1 x 15284818.05. 03:36
r6s0x86_​642 x 10 x 21,700136,18018.05. 03:39
r6s1x86_​642 x 12,0007,97818.05. 03:40
r6s2x86_​642 x 11,6679,57818.05. 03:42
r6s3x86_​644 x 22,20035,12018.05. 03:43
r6s4x86_​642 x 11,1004,37618.05. 03:45
r6s5i6861 x 11,5002,99218.05. 03:47
r6s6i6861 x 11,6003,19118.05. 03:50
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35618.05. 03:51
r7s0x86_​642 x 22,30018,40018.05. 03:52
r7s1x86_​644 x 11,60012,84017.05. 16:06
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700517.05. 16:08
r7s3sarm​v7l4 x 11,40035617.05. 16:11
r7s4arm​v7l1 x 153634817.05. 16:14
r7s4sarm​v7l4 x 11,5001,08017.05. 16:16
r7s5i6861 x 11,3002,59317.05. 04:12
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76717.05. 16:17
r7s7sx86_​642 x 22,30018,39617.05. 16:19
r7s8arm​v7l1 x 11,00099517.05. 16:21
r7s8sarm​v7l1 x 11,00059717.05. 16:23
r8s0x86_​642 x 22,30018,40017.05. 16:24
r8s1i5861 x 135070117.05. 16:25
r8s2x86_​642 x 22,10016,76017.05. 16:27
r8s2sx86_​642 x 22,10016,76017.05. 16:29
r8s3x86_​644 x 12,66721,28017.05. 16:30
r8s4x86_​644 x 21,60028,80017.05. 16:32
r8s4sx86_​644 x 21,60028,80017.05. 16:34
r8s5i6864 x 23,40054,40017.05. 16:36
r8s6arm​v7l1 x 150049817.05. 16:38
r8s7x86_​642 x 12,70010,77617.05. 16:39
r8s7sx86_​642 x 13,30013,19817.05. 16:40
r8s8x86_​642 x 11,3005,14417.05. 16:42
r9s0x86_​642 x 22,30018,40017.05. 16:45
r9s1x86_​642 x 12,0003,99217.05. 16:46
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74817.05. 16:48
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74817.05. 16:50
r9s3sx86_​644 x 13,00024,00017.05. 16:51
r9s4i6861 x 21,0003,99017.05. 16:54
r9s4sx86_​642 x 11,3335,34717.05. 17:00
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99817.05. 17:02
r9s6x86_​642 x 23,00023,94417.05. 17:04
r9s7arm​v7l2 x 11,000017.05. 17:06
r9s8sarm​v7l1 x 180079617.05. 17:07
ras0x86_​642 x 22,30018,41617.05. 17:08
ras1i6861 x 11,4002,79917.05. 17:10
ras2x86_​642 x 11,0674,26617.05. 17:11
ras3aarch​648 x 12,0004,00017.05. 17:12
ras3sarm​v7l1 x 11,30084017.05. 17:13
ras4arm​v7l1 x 150039817.05. 17:14
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002417.05. 17:15
ras5sarm​v7l2 x 11,0002417.05. 17:16
ras6aarch​648 x 12,0003,20017.05. 17:17
ras6sarm​v7l1 x 11,0001,98717.05. 17:18
ras7ppc1 x 13966517.05. 17:19
ras8x86_​644 x 11,60014,40017.05. 17:20
ras8sx86_​644 x 11,60012,74817.05. 17:22
rbs0i6862 x 22,50017,60017.05. 17:24
rbs1x86_​644 x 12,00015,97217.05. 17:25
rbs2x86_​644 x 12,00015,97217.05. 17:26
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962817.05. 05:21
rbs3sarm​v7l4 x 11,40035617.05. 17:27
rbs4x86_​644 x 11,2009,60017.05. 17:30
rbs4sx86_​644 x 11,60012,74817.05. 17:32
rbs5i6864 x 2049,53917.05. 17:33
rbs5saarch​644 x 11,6006417.05. 17:34
rbs6x86_​644 x 11,91515,32417.05. 17:36
rbs6sx86_​642 x 11,3335,33217.05. 17:37
rbs7arm​v7l4 x 19962817.05. 17:39
rbs7sarm​v7l4 x 19962417.05. 17:41
rbs8arm​v7l2 x 16662,65017.05. 17:44
rbs8sx86_​644 x 22,40038,70417.05. 17:45
rcs0x86_​648 x 22,40076,60017.05. 17:49
rcs1x86_​646 x 23,46783,37617.05. 17:51
rcs2x86_​642 x 12,80011,23217.05. 17:54
rcs3i6862 x 11,4005,58617.05. 17:56
rcs3sx86_​644 x 23,30052,69617.05. 17:58
rcs4x86_​642 x 11,1004,37617.05. 18:01
rcs4sx86_​644 x 11,1008,75217.05. 18:03
rcs5x86_​642 x 12,80011,19817.05. 18:05
rcs5sx86_​642 x 12,80011,19817.05. 18:07
rcs6x86_​644 x 23,50063,99211.05. 17:51
rcs7x86_​642 x 21,80014,39617.05. 18:09
rcs7sx86_​644 x 11,50011,98017.05. 18:11
rcs8x86_​6416 x 23,700217,15217.05. 18:17
rcs8sx86_​644 x 23,30052,79217.05. 18:19
rds0x86_​644 x 21,80031,99217.05. 18:21
rds1x86_​644 x 11,91015,32417.05. 18:22
rds2x86_​644 x 11,91015,32417.05. 18:23
rds3x86_​644 x 11,91015,32417.05. 18:25
rds4x86_​644 x 11,91015,32417.05. 18:26
rds5x86_​644 x 11,60012,74817.05. 18:28
rds6x86_​644 x 11,60012,74817.05. 18:30
rds7x86_​644 x 11,60012,74817.05. 18:31
rds8x86_​644 x 11,60012,74817.05. 18:32
res0x86_​644 x 21,80031,99217.05. 18:33
res1x86_​644 x 11,60014,40017.05. 18:35
res1sx86_​644 x 11,60014,40017.05. 18:37
res2x86_​644 x 11,60014,40017.05. 18:38
res3x86_​644 x 12,00015,97217.05. 18:39
res3saarch​640 x 1 x 11,0001,60017.05. 18:41
res4x86_​644 x 11,90015,05217.05. 18:42
res4sx86_​644 x 11,90015,05217.05. 18:44
res5x86_​642 x 22,20019,20017.05. 18:45
res5sx86_​642 x 22,20019,20017.05. 18:48
res6x86_​644 x 11,1008,75217.05. 18:50
res6saarch​644 x 101,60017.05. 18:52
res7arm​v7l0 x 1 x 11,0001217.05. 18:55
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05217.05. 18:56
res8sx86_​644 x 11,90015,05217.05. 18:58
rfs0x86_​6416 x 22,000128,00017.05. 19:00
rfs1aarch​644 x 11,50043217.05. 19:01
rfs2aarch​644 x 11,50043217.05. 19:02
rfs4arm​v7l1 x 180080017.05. 19:03
rfs4sarm​v7l1 x 180080017.05. 19:10
rfs6arm​v7l1 x 16671,33218.05. 02:03
rfs6sarm​v7l1 x 16671,33218.05. 02:04
 

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