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2026-04-13 - 02:52

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50039,99213.04. 01:10
r0s0sx86_​644 x 23,40054,39213.04. 01:10
r0s1x86_​644 x 22,30056,00013.04. 01:11
r0s1sx86_​644 x 23,30052,80013.04. 01:11
r0s2x86_​644 x 23,50055,86413.04. 01:11
r0s2sx86_​6410 x 13,70073,99013.04. 01:12
r0s3x86_​648 x 23,600115,20013.04. 01:13
r0s3sx86_​644 x 23,60067,20013.04. 01:14
r0s4x86_​648 x 23,600115,20013.04. 01:14
r0s4sx86_​648 x 23,600115,20013.04. 01:15
r0s5x86_​648 x 23,500115,20013.04. 01:15
r0s5sx86_​648 x 23,600115,20013.04. 01:16
r0s6x86_​648 x 23,600115,20013.04. 01:17
r0s6sx86_​6410 x 23,700147,98013.04. 01:17
r0s7x86_​648 x 23,600115,20006.01. 13:20
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20014.03. 13:20
r0s8sx86_​646 x 23,47083,38813.04. 01:18
r1s0x86_​644 x 13,10024,80013.04. 01:19
r1s1x86_​642 x 22,60021,69613.04. 01:20
r1s2x86_​644 x 12,30027,99613.04. 01:20
r1s2sx86_​644 x 12,30028,00013.04. 01:21
r1s3x86_​644 x 12,80022,42413.04. 01:21
r1s4arm​v7l2 x 11,2004813.04. 01:22
r1s4sarm​v7l2 x 14004813.04. 01:22
r1s5aarch​644 x 11,20079613.04. 01:23
r1s6x86_​642 x 22,13017,06413.04. 01:23
r1s6sx86_​642 x 21,66713,33213.04. 01:24
r1s7arm​v6l1 x 11,66753013.04. 01:25
r1s8i6861 x 21,6006,40013.04. 01:25
r1s8sx86_​644 x 11,90015,19613.04. 01:26
r2s0x86_​644 x 13,10024,79613.04. 01:26
r2s1arm​v5tejl1 x 120019913.04. 01:27
r2s2arm​v7l1 x 172049913.04. 01:27
r2s3arm​v7l0 x 1 x 162462413.04. 01:27
r2s3sarm​v7l0 x 2 x 16001,20013.04. 01:28
r2s4mips​641 x 180053129.09. 13:34
r2s5ppc1 x 13966625.12. 13:33
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r2s6i6861 x 11,5002,99913.04. 01:29
r2s6saarch​644 x 11,3506413.04. 01:30
r2s7aarch​644 x 12,40043213.04. 01:30
r2s7saarch​644 x 11,50043213.04. 01:31
r2s8ppc1 x 14006613.04. 01:32
r3s0i6864 x 23,50055,99213.04. 01:33
r3s1i6864 x 12,40019,12813.04. 01:33
r3s2riscv641 x 11,00028413.04. 01:34
r3s2sriscv644 x 1028413.04. 01:35
r3s3x86_​646 x 23,33379,99213.04. 01:35
r3s3sx86_​644 x 13,40011,98013.04. 01:36
r3s4aarch​646 x 11,3009613.04. 01:36
r3s5i5861 x 113326513.04. 01:38
r3s5sppc2 x 11,20040013.04. 01:39
r3s6x86_​641 x 21,6606,66613.04. 01:40
r3s6sx86_​642 x 22,66721,33213.04. 01:40
r3s7i6861 x 15331,06613.04. 01:41
r4s0x86_​642 x 22,30018,40013.04. 01:42
r4s1arm​v7l4 x 11,50072013.04. 01:43
r4s1sarm​v7l4 x 11,50093613.04. 01:43
r4s2arm​v7l1 x 180079613.04. 01:44
r4s2sarm​v7l1 x 180053013.04. 01:45
r4s3i5861 x 150099613.04. 01:47
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049813.04. 01:48
r4s5arm​v7l1 x 1500013.04. 01:51
r4s5saarch​644 x 11,60020013.04. 01:52
r4s6x86_​644 x 23,40054,25613.04. 01:52
r4s6sarm​v7l0 x 1 x 11,0006613.04. 01:52
r4s7i6864 x 11,83314,66413.04. 01:53
r4s7sx86_​642 x 11,8337,33213.04. 01:54
r4s8arm​v7l1 x 140039813.04. 01:55
r4s8sarm​v7l1 x 140039813.04. 01:55
r5s0x86_​642 x 22,20017,58413.04. 01:56
r5s1x86_​646 x 13,33340,08613.04. 01:56
r5s2x86_​644 x 12,70021,69913.04. 01:57
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87213.04. 01:57
r5s3sx86_​644 x 11,60012,74813.04. 01:58
r5s4x86_​642 x 22,53020,26413.04. 01:59
r5s4sx86_​644 x 11,60012,74813.04. 02:00
r5s5arm​v7l1 x 160059713.04. 02:01
r5s5sarm​v7l1 x 160060013.04. 02:03
r5s6ppc1 x 153313313.04. 02:06
r5s7arm​v7l1 x 15286413.04. 02:07
r5s7sarm​v7l1 x 15284813.04. 02:09
r5s8x86_​644 x 12,00015,97213.04. 02:10
r6s0x86_​642 x 10 x 21,700136,14013.04. 02:11
r6s1x86_​642 x 12,0007,97812.12. 02:21
r6s2x86_​642 x 11,6679,57813.04. 02:11
r6s3x86_​644 x 22,20035,12013.04. 02:12
r6s4x86_​642 x 11,1004,37613.04. 02:13
r6s5i6861 x 11,5002,99213.04. 02:14
r6s6i6861 x 11,6003,19213.04. 02:15
r6s7i6862 x 12,3009,17613.04. 02:15
r6s8x86_​642 x 22,30018,35613.04. 02:16
r7s0x86_​642 x 22,30018,40013.04. 02:16
r7s1x86_​644 x 11,60012,83913.04. 02:17
r7s2aarch​642 x 11,7009613.04. 02:17
r7s2sriscv644 x 1028413.04. 02:18
r7s3arm​v6l1 x 1700513.04. 02:19
r7s3sarm​v7l4 x 11,40035613.04. 02:21
r7s4arm​v7l1 x 153634802.04. 14:22
r7s4sarm​v7l4 x 11,5001,08013.04. 02:22
r7s5i6861 x 11,3002,59313.04. 02:23
r7s7x86_​644 x 11,60012,76713.04. 02:23
r7s7sx86_​642 x 22,30018,39613.04. 02:24
r7s8arm​v7l1 x 11,00099513.04. 02:25
r7s8sarm​v7l1 x 11,00099613.04. 02:26
r8s0x86_​642 x 22,30018,40013.04. 02:27
r8s1i5861 x 135070113.04. 02:28
r8s3x86_​644 x 12,66721,28013.04. 02:29
r8s4x86_​644 x 21,60028,80013.04. 02:29
r8s4sx86_​644 x 21,60028,80013.04. 02:30
r8s5i6864 x 23,40054,40013.04. 02:30
r8s6arm​v7l1 x 150049813.04. 02:31
r8s6sx86_​644 x 13,30026,41613.04. 02:31
r8s7x86_​644 x 13,20025,49613.04. 02:32
r8s7sx86_​642 x 13,00011,98013.04. 02:33
r8s8x86_​642 x 11,3005,14413.04. 02:33
r9s0x86_​644 x 23,60057,60013.04. 02:34
r9s1x86_​642 x 12,0007,98412.02. 14:30
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74813.04. 02:35
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74813.04. 02:36
r9s3sx86_​644 x 13,00024,00013.04. 02:36
r9s4i6861 x 21,0003,99013.04. 02:37
r9s4sx86_​642 x 11,3335,34713.04. 02:37
r9s5sx86_​642 x 13,30013,19813.04. 02:38
r9s6x86_​642 x 23,00023,94413.04. 02:39
r9s7arm​v7l2 x 11,000013.04. 02:39
r9s8sarm​v7l1 x 180079613.04. 02:40
ras0x86_​642 x 22,30018,41813.04. 02:40
ras1i6861 x 11,4002,79913.04. 02:41
ras2x86_​642 x 11,0674,26613.04. 02:41
ras2sx86_​644 x 11,90015,05213.04. 02:42
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084013.04. 02:42
ras4aarch​648 x 12,40038413.04. 02:43
ras4saarch​648 x 12,40038429.09. 03:02
ras5arm​v7l2 x 11,0002413.04. 02:43
ras5sarm​v7l2 x 11,0002413.04. 02:44
ras6aarch​648 x 12,0003,20013.04. 02:44
ras6sarm​v7l1 x 11,0001,98713.04. 02:45
ras7ppc1 x 13966513.04. 02:46
ras8x86_​644 x 11,60014,40013.04. 02:46
ras8sx86_​644 x 11,60012,74813.04. 02:46
rbs0i6862 x 22,50017,60013.04. 02:47
rbs3arm​v7l4 x 19962412.04. 14:46
rbs3sarm​v7l4 x 11,40035613.04. 02:48
rbs4x86_​644 x 11,2009,60013.04. 02:49
rbs4sx86_​644 x 11,60012,74813.04. 02:49
rbs5i6864 x 2052,36513.04. 02:50
rbs5saarch​644 x 11,6006413.04. 02:50
rbs6x86_​644 x 11,91515,32413.04. 02:50
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961213.04. 02:51
rbs7sarm​v7l4 x 19962412.04. 14:52
rbs8arm​v7l2 x 16662,65012.04. 14:53
rbs8sx86_​644 x 22,40038,70412.04. 14:53
rcs0x86_​648 x 22,40076,40012.04. 14:55
rcs1x86_​646 x 23,46783,37612.04. 14:56
rcs2x86_​642 x 12,80011,23212.04. 14:56
rcs3i6862 x 11,4005,58612.04. 14:57
rcs3sx86_​644 x 13,30026,39612.04. 14:57
rcs4x86_​642 x 11,1004,37612.04. 14:58
rcs5x86_​642 x 12,80011,19812.04. 14:59
rcs5sx86_​642 x 12,80011,19812.04. 15:00
rcs6x86_​644 x 23,50063,99212.04. 15:01
rcs7x86_​642 x 21,80014,40012.04. 15:02
rcs7sx86_​644 x 11,50011,98012.04. 15:03
rcs8x86_​6416 x 23,700217,18412.04. 15:06
rcs8sx86_​644 x 23,30052,80012.04. 15:07
rds0x86_​644 x 21,80031,99212.04. 15:07
rds1x86_​644 x 11,60012,74812.04. 15:08
rds2x86_​644 x 11,60012,74812.04. 15:09
rds3x86_​644 x 11,60012,74812.04. 15:09
rds4x86_​644 x 11,60012,74812.04. 15:10
rds5x86_​644 x 11,60012,74812.04. 15:10
rds6x86_​644 x 11,60012,74812.04. 15:11
rds7x86_​644 x 11,60012,74812.04. 15:11
rds8x86_​644 x 11,60012,74812.04. 15:12
res0x86_​644 x 23,40054,39212.04. 15:12
res1x86_​644 x 11,60014,40012.04. 15:13
res1sx86_​644 x 11,60014,40012.04. 15:14
res2x86_​644 x 11,60014,40012.04. 15:14
res3x86_​644 x 12,00015,97212.04. 15:15
res3saarch​640 x 1 x 11,0001,60012.04. 15:15
res4x86_​644 x 11,90015,05212.04. 15:16
res4sx86_​644 x 11,90015,05212.04. 15:16
res5x86_​642 x 22,20019,20012.04. 15:17
res5sx86_​642 x 22,20019,20012.04. 15:17
res6x86_​644 x 11,1008,75212.04. 15:18
res6saarch​644 x 101,60012.04. 15:19
res7arm​v7l0 x 1 x 11,0001212.04. 15:19
res7sarm​v7l0 x 1 x 11,0001212.04. 15:21
res8x86_​644 x 11,90015,05212.04. 15:21
res8sx86_​644 x 11,90015,05212.04. 15:22
rfs0x86_​6416 x 22,000128,00012.04. 15:22
rfs1aarch​644 x 11,50043212.04. 15:23
rfs1saarch​644 x 11,50043212.04. 15:23
rfs2x86_​644 x 13,00024,00012.04. 15:23
rfs2sx86_​642 x 13,00011,99812.04. 15:24
rfs3x86_​644 x 11,60012,74812.04. 15:24
rfs3sx86_​644 x 11,60012,74812.04. 15:25
rfs4aarch​641 x 11,4001,60012.04. 15:25
rfs4sarm​v7l1 x 180080012.04. 15:26
rfs5aarch​644 x 11,2006412.04. 15:27
rfs5saarch​644 x 11,2006412.04. 15:28
rfs6arm​v7l1 x 16671,33212.04. 15:29
rfs6sarm​v7l1 x 16671,33212.04. 15:30
rfs7x86_​644 x 22,60041,60012.04. 15:30
rfs7sx86_​644 x 17006,44812.04. 15:31
rfs8arm​v7l1 x 11,00012012.04. 15:31
 

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