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2024-05-07 - 15:24

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OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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Number of cores/hyperthreads and bogoMIPS (by arch) - (x86 CPU strings)

BoxArch ↑CoresMHzBogo​MIPSEffective
ras6aarch​648 x 12,0003,20007.05. 04:44
res3saarch​640 x 1 x 11,0001,60007.05. 05:58
r4s5saarch​644 x 11,60020027.03. 14:13
r2s6saarch​644 x 11,3506407.05. 14:05
r2s7aarch​644 x 12,40043207.05. 14:06
res6saarch​644 x 101,60007.05. 06:06
rbs5saarch​644 x 11,6006407.05. 05:01
r1s5aarch​644 x 11,20079607.05. 13:52
rfs1aarch​644 x 11,50043207.05. 06:11
rfs2aarch​644 x 11,50043207.05. 06:12
r2s7saarch​644 x 11,50043207.05. 14:08
r3s4aarch​646 x 11,3009607.05. 14:17
ras3aarch​648 x 12,0004,00007.05. 04:40
r2s1arm​v5tejl1 x 120019907.05. 14:00
r1s7arm​v6l1 x 120053007.05. 13:55
r7s3arm​v6l1 x 1700507.05. 03:37
r2s2arm​v7l1 x 172049907.05. 14:01
r1s4arm​v7l2 x 11,2004807.05. 13:50
r4s2sarm​v7l1 x 180053007.05. 14:37
r7s8arm​v7l1 x 11,00099507.05. 03:51
ras5arm​v7l2 x 11,0002407.05. 04:42
r7s4arm​v7l1 x 153634807.05. 03:43
r4s2arm​v7l1 x 180079607.05. 14:35
rbs3arm​v7l4 x 19962407.05. 04:55
r7s3sarm​v7l4 x 11,40035607.05. 03:41
ras4arm​v7l1 x 150039807.05. 04:41
r7s4sarm​v7l4 x 11,5001,08007.05. 03:45
r4s8sarm​v7l1 x 140039807.05. 14:56
rfs4sarm​v7l1 x 180080007.05. 06:18
r4s1sarm​v7l4 x 11,5001,08007.05. 14:33
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002407.05. 04:43
r4s1arm​v7l4 x 11,5001,08007.05. 14:31
res7arm​v7l0 x 1 x 11,0001207.05. 06:08
rbs7sarm​v7l4 x 19962407.05. 05:07
rfs4arm​v7l1 x 180080007.05. 06:13
ras3sarm​v7l1 x 11,30084007.05. 04:40
r7s8sarm​v7l1 x 11,00099607.05. 03:53
r9s7arm​v7l2 x 11,000007.05. 04:33
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r1s4sarm​v7l2 x 14004807.05. 13:51
r8s6arm​v7l1 x 150049807.05. 04:08
r5s5sarm​v7l1 x 160060001.05. 15:04
r2s3sarm​v7l0 x 1 x 16001,20007.05. 14:02
rbs3sarm​v7l4 x 11,40015207.05. 04:55
r5s7arm​v7l1 x 15284807.05. 15:10
r9s1sarm​v7l1 x 101,25014.04. 18:03
rbs7arm​v7l4 x 19962807.05. 05:06
r5s5arm​v7l1 x 160059707.05. 15:08
ras4sarm​v7l1 x 160059707.02. 02:45
rbs8arm​v7l2 x 16662,65007.05. 05:09
r4s5arm​v7l1 x 1500007.05. 14:47
r4s6sarm​v7l0 x 1 x 11,0006607.05. 14:51
r4s8arm​v7l1 x 140039807.05. 14:56
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r5s7sarm​v7l1 x 15286407.05. 15:12
r2s3arm​v7l0 x 1 x 162462407.05. 14:01
ras6sarm​v7l1 x 11,0001,98707.05. 04:46
r9s8sarm​v7l1 x 180079607.05. 04:35
r4s3i5861 x 150099607.05. 14:41
r8s1i5861 x 135070107.05. 03:56
r3s5i5861 x 113326507.05. 14:22
r9s4i6861 x 21,0003,99007.05. 04:22
r3s8i6866 x 13,20038,52607.05. 14:29
rbs5i6864 x 2049,53907.05. 05:01
r6s6i6861 x 11,6003,19107.05. 15:23
r2s6i6861 x 11,5002,99907.05. 14:04
r6s5i6861 x 11,5001,12207.05. 15:21
rbs0i6862 x 22,50017,60007.05. 04:51
ras1i6861 x 11,4002,79907.05. 04:37
r4s3si6861 x 11,4662,93207.05. 14:43
r7s5i6861 x 11,3002,59307.05. 03:46
r3s0i6864 x 23,50055,99207.05. 14:11
r1s8i6861 x 21,6006,39807.05. 13:56
r6s7i6862 x 12,3009,17611.01. 02:44
r8s5i6864 x 23,40054,40007.05. 04:06
rcs3i6862 x 11,4005,58607.05. 05:18
r3s1i6864 x 12,40019,12707.05. 14:12
r3s7i6861 x 15331,06607.05. 14:28
r4s7i6864 x 11,83314,66407.05. 14:53
r2s4mips​641 x 180053124.12. 13:46
r5s6ppc1 x 153313307.05. 15:10
r2s8ppc1 x 14006607.05. 14:09
ras7ppc1 x 13966507.05. 04:47
r2s5ppc1 x 13966627.03. 13:43
r4s4ppc4 x 11,20049807.05. 14:44
r3s5sppc2 x 11,20040007.05. 14:24
r3s2sriscv644 x 1028407.05. 14:15
r3s2riscv641 x 11,00028407.05. 14:13
rds3x86_​644 x 11,91015,32407.05. 05:46
ras0x86_​642 x 22,30018,41607.05. 04:36
r9s3x86_​644 x 11,60012,74807.05. 04:19
r0s4x86_​648 x 23,600115,20007.05. 13:21
r6s0x86_​642 x 10 x 21,700136,18007.05. 15:15
rbs8sx86_​644 x 22,40038,70407.05. 05:11
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r9s2x86_​644 x 11,60012,74807.05. 04:17
r9s5sx86_​642 x 13,50013,99807.05. 04:29
r1s0x86_​644 x 13,10024,79607.05. 13:43
rcs7sx86_​644 x 11,50011,98007.05. 05:33
r1s8sx86_​644 x 11,90015,19607.05. 13:57
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s0x86_​642 x 22,30018,40007.05. 04:15
rds6x86_​644 x 11,60012,74807.05. 05:49
res8sx86_​644 x 11,90015,05206.05. 18:09
r5s3x86_​644 x 22,00031,87207.05. 03:03
ras8sx86_​644 x 11,60012,74807.05. 04:50
r0s7x86_​648 x 23,600115,20007.05. 13:33
r0s2sx86_​6410 x 13,70073,99007.05. 13:14
r5s2x86_​644 x 12,70021,69907.05. 15:00
rfs0x86_​6416 x 22,000128,00007.05. 06:10
r0s8x86_​648 x 23,600115,20007.05. 13:40
rbs4sx86_​644 x 11,60012,74807.05. 04:59
rcs4sx86_​644 x 11,1008,75207.05. 05:25
r9s4sx86_​642 x 11,3335,34707.05. 04:28
r1s3x86_​644 x 12,80022,42407.05. 13:48
res2x86_​644 x 11,60014,40007.05. 05:56
r8s7sx86_​642 x 13,30013,19807.05. 04:10
r5s1x86_​646 x 13,33340,09207.05. 14:58
rcs6x86_​644 x 23,50063,99207.05. 05:30
rcs1x86_​646 x 23,46783,37607.05. 05:16
r0s1sx86_​644 x 23,30052,67207.05. 13:12
r0s0x86_​644 x 22,50040,00007.05. 13:10
res8x86_​644 x 11,90015,05207.05. 06:09
res1x86_​644 x 11,60014,40007.05. 05:55
r6s8x86_​642 x 22,30018,35607.05. 03:34
r0s2x86_​644 x 23,50055,86407.05. 13:13
rds8x86_​644 x 11,60012,74807.05. 05:52
rbs4x86_​644 x 11,2009,60007.05. 04:58
r4s6x86_​644 x 23,40054,25607.05. 14:48
r3s6sx86_​642 x 22,66721,33207.05. 14:27
rbs2x86_​644 x 12,00015,97207.05. 04:53
r0s3x86_​648 x 23,600115,20007.05. 13:15
res4sx86_​644 x 11,90015,05207.05. 06:01
r4s7sx86_​642 x 11,8337,33207.05. 14:54
r0s7sx86_​642 x 23,70029,52807.05. 13:38
res6x86_​644 x 11,1008,75207.05. 06:05
r0s5x86_​648 x 23,500115,20007.05. 13:25
r8s0x86_​642 x 22,30018,40007.05. 03:54
r5s3sx86_​644 x 11,60012,74807.05. 15:02
r6s3x86_​644 x 22,20035,12007.05. 15:18
r7s1x86_​644 x 11,60012,84007.05. 03:36
rbs1x86_​644 x 12,00015,97207.05. 04:52
rds4x86_​644 x 11,91015,32407.05. 05:47
rcs8sx86_​644 x 23,30052,79207.05. 05:40
r6s2x86_​642 x 11,6679,57807.05. 15:17
rcs8x86_​6416 x 23,700217,15207.05. 05:39
r8s4x86_​644 x 21,60028,80007.05. 04:02
rcs0x86_​648 x 22,40076,60007.05. 05:15
rbs6sx86_​642 x 11,3335,33207.05. 05:04
r9s3sx86_​644 x 13,00024,00007.05. 04:20
r1s1x86_​642 x 22,60021,69607.05. 13:44
res4x86_​644 x 11,90015,05207.05. 05:59
r8s7x86_​642 x 12,70010,77607.05. 04:09
r0s8sx86_​646 x 23,47083,38807.05. 13:41
r5s4sx86_​642 x 22,53020,26407.05. 15:05
r8s8x86_​642 x 11,3005,14407.05. 04:12
r7s7sx86_​642 x 22,30018,39607.05. 03:49
ras2x86_​642 x 11,0674,26607.05. 04:38
rds2x86_​644 x 11,91015,32407.05. 05:45
r4s0x86_​642 x 22,30018,39607.05. 14:30
res3x86_​644 x 12,00015,97207.05. 05:57
r8s2x86_​642 x 22,10016,76007.05. 03:57
rbs6x86_​644 x 11,91515,32407.05. 05:02
r0s1x86_​644 x 22,30055,99207.05. 13:11
r3s3x86_​646 x 23,33379,99207.05. 14:16
r9s2sx86_​644 x 11,60012,74830.08. 17:02
rcs5sx86_​642 x 12,80011,19807.05. 05:29
res0x86_​644 x 21,80031,99207.05. 05:53
r5s0x86_​642 x 22,20017,58207.05. 14:57
r8s4sx86_​644 x 21,60028,80007.05. 04:04
rcs3sx86_​644 x 23,30052,69607.05. 05:21
r9s1x86_​642 x 12,0003,99207.05. 04:16
r7s7x86_​644 x 11,60012,76707.05. 03:47
res5sx86_​642 x 22,20019,20007.05. 06:03
r9s6x86_​642 x 23,00023,94407.05. 04:31
r1s6x86_​642 x 22,13017,06407.05. 13:53
rcs7x86_​642 x 21,80014,39607.05. 05:32
r1s2sx86_​644 x 12,30028,00007.05. 13:47
r0s6sx86_​6410 x 23,700147,98007.05. 13:31
r3s6x86_​641 x 11,6603,33307.05. 14:25
r1s6sx86_​642 x 21,66713,33207.05. 13:54
rds0x86_​644 x 21,80031,99207.05. 05:43
rcs5x86_​642 x 12,80011,19807.05. 05:27
res1sx86_​644 x 11,60014,40007.05. 05:55
rds7x86_​644 x 11,60012,74807.05. 05:51
r5s2sx86_​644 x 24,00063,86312.04. 01:34
rcs2x86_​642 x 12,80011,23207.05. 05:17
r5s4x86_​642 x 22,53020,26407.05. 15:03
rcs4x86_​642 x 11,1004,37607.05. 05:24
r8s3x86_​644 x 12,66721,28007.05. 04:01
r2s0x86_​644 x 13,10024,80007.05. 13:58
r1s2x86_​644 x 12,30028,00007.05. 13:45
r0s3sx86_​644 x 23,60067,20007.05. 13:20
r6s1x86_​642 x 12,0007,97807.05. 15:16
r7s0x86_​642 x 22,30018,40007.05. 03:35
rds1x86_​644 x 11,91015,32407.05. 05:44
r0s6x86_​648 x 23,600115,20007.05. 13:29
r8s2sx86_​642 x 22,10016,76007.05. 03:58
r0s4sx86_​648 x 23,600115,20007.05. 13:23
rbs2sx86_​641 x 13,500007.09. 15:06
r6s4x86_​642 x 11,1004,37607.05. 15:20
rds5x86_​644 x 11,60012,74807.05. 05:48
ras8x86_​644 x 11,60014,40007.05. 04:48
res5x86_​642 x 22,20019,20007.05. 06:02
r0s5sx86_​648 x 23,600115,20007.05. 13:26
 

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