You are here: Home / Projects / OSADL QA Farm Real-time / CPUs under test / 
2024-05-16 - 09:32

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,53916.05. 05:27
r9s1sarm​v7l1 x 101,25014.04. 18:03
r3s2sriscv644 x 1028416.05. 02:21
res6saarch​644 x 101,60016.05. 06:35
r3s5i5861 x 113326516.05. 02:30
r2s1arm​v5tejl1 x 120019916.05. 02:03
r8s1i5861 x 135070116.05. 04:22
r2s5ppc1 x 13966627.03. 13:43
ras7ppc1 x 13966516.05. 05:14
r1s4sarm​v7l2 x 14004816.05. 01:52
r4s8arm​v7l1 x 140039816.05. 03:11
r2s8ppc1 x 14006616.05. 02:14
r4s8sarm​v7l1 x 140039816.05. 03:13
r8s6arm​v7l1 x 150049816.05. 04:34
r4s5arm​v7l1 x 1500016.05. 03:00
r4s3i5861 x 150099616.05. 02:52
ras4arm​v7l1 x 150039816.05. 05:09
r5s7sarm​v7l1 x 15286416.05. 03:40
r5s7arm​v7l1 x 15286416.05. 03:37
r3s7i6861 x 15331,06616.05. 02:37
r5s6ppc1 x 153313316.05. 03:36
r7s4arm​v7l1 x 153634816.05. 04:08
r5s5sarm​v7l1 x 160060016.05. 03:31
r2s3sarm​v7l0 x 1 x 16001,20016.05. 02:06
r5s5arm​v7l1 x 160059716.05. 03:27
ras4sarm​v7l1 x 160059707.02. 02:45
r2s3arm​v7l0 x 1 x 162462416.05. 02:04
rbs8arm​v7l2 x 16662,65016.05. 05:35
r7s3arm​v6l1 x 1700516.05. 04:02
r2s2arm​v7l1 x 172049916.05. 02:03
rfs4arm​v7l1 x 180080016.05. 06:44
r9s8sarm​v7l1 x 180079616.05. 05:01
r4s2sarm​v7l1 x 180053016.05. 02:48
r4s2arm​v7l1 x 180079616.05. 02:45
rfs4sarm​v7l1 x 180080016.05. 06:51
r2s4mips​641 x 180053124.12. 13:46
rbs7arm​v7l4 x 19962816.05. 05:32
rbs3arm​v7l4 x 19962816.05. 05:21
rbs7sarm​v7l4 x 19962416.05. 05:34
r9s4i6861 x 21,0003,99016.05. 04:47
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r3s2riscv641 x 11,00028416.05. 02:20
r4s6sarm​v7l0 x 1 x 11,0006616.05. 03:05
ras6sarm​v7l1 x 11,0001,98716.05. 05:13
r7s8arm​v7l1 x 11,00099516.05. 04:17
ras5arm​v7l2 x 11,0002416.05. 05:10
res3saarch​640 x 1 x 11,0001,60016.05. 06:27
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002416.05. 05:10
res7arm​v7l0 x 1 x 11,0001216.05. 06:37
r7s8sarm​v7l1 x 11,00059716.05. 04:19
r9s7arm​v7l2 x 11,000016.05. 05:00
ras2x86_​642 x 11,0674,26616.05. 05:06
rcs4x86_​642 x 11,1004,37616.05. 05:50
r6s4x86_​642 x 11,1004,37616.05. 03:50
rcs4sx86_​644 x 11,1008,75216.05. 05:51
res6x86_​644 x 11,1008,75216.05. 06:33
r4s4ppc4 x 11,20049816.05. 02:56
r1s5aarch​644 x 11,20079616.05. 01:53
r3s5sppc2 x 11,20040016.05. 02:33
r1s4arm​v7l2 x 11,2004816.05. 01:51
rbs4x86_​644 x 11,2009,60016.05. 05:25
ras3sarm​v7l1 x 11,30084016.05. 05:08
r3s4aarch​646 x 11,3009616.05. 02:25
r7s5i6861 x 11,3002,59316.05. 04:12
r8s8x86_​642 x 11,3005,14416.05. 04:39
rbs6sx86_​642 x 11,3335,33216.05. 05:30
r9s4sx86_​642 x 11,3335,34716.05. 04:53
r2s6saarch​644 x 11,3506416.05. 02:09
rcs3i6862 x 11,4005,58616.05. 05:45
rbs3sarm​v7l4 x 11,40035616.05. 05:22
r7s3sarm​v7l4 x 11,40035616.05. 04:05
ras1i6861 x 11,4002,79916.05. 05:04
r4s3si6861 x 11,4662,93216.05. 02:55
r2s7saarch​644 x 11,50043216.05. 02:12
rfs1aarch​644 x 11,50043216.05. 06:43
rfs2aarch​644 x 11,50043216.05. 06:43
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rcs7sx86_​644 x 11,50011,98016.05. 05:59
r2s6i6861 x 11,5002,99916.05. 02:07
r6s5i6861 x 11,5002,99216.05. 03:52
r7s4sarm​v7l4 x 11,5001,08016.05. 04:10
r4s1sarm​v7l4 x 11,5001,08016.05. 02:42
r4s1arm​v7l4 x 11,5001,08016.05. 02:40
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80016.05. 04:30
r7s7x86_​644 x 11,60012,76716.05. 04:13
res1sx86_​644 x 11,60014,40016.05. 06:23
rds7x86_​644 x 11,60012,74816.05. 06:18
rds5x86_​644 x 11,60012,74816.05. 06:15
ras8x86_​644 x 11,60014,40016.05. 05:15
r9s3x86_​644 x 11,60012,74816.05. 04:44
r9s2x86_​644 x 11,60012,74816.05. 04:42
rds6x86_​644 x 11,60012,74816.05. 06:17
ras8sx86_​644 x 11,60012,74816.05. 05:16
rbs4sx86_​644 x 11,60012,74816.05. 05:26
res2x86_​644 x 11,60014,40016.05. 06:24
r6s6i6861 x 11,6003,19116.05. 03:55
res1x86_​644 x 11,60014,40016.05. 06:22
rds8x86_​644 x 11,60012,74816.05. 06:19
r4s5saarch​644 x 11,60020027.03. 14:13
r5s3sx86_​644 x 11,60012,74816.05. 03:20
r7s1x86_​644 x 11,60012,84016.05. 04:00
r8s4x86_​644 x 21,60028,80016.05. 04:29
rbs5saarch​644 x 11,6006416.05. 05:28
r1s8i6861 x 21,6006,39816.05. 01:58
r3s6x86_​641 x 11,6603,33316.05. 02:34
r1s6sx86_​642 x 21,66713,33216.05. 01:55
r6s2x86_​642 x 11,6679,57816.05. 03:46
r6s0x86_​642 x 10 x 21,700136,18016.05. 03:42
res0x86_​644 x 21,80031,99216.05. 06:20
r1s7arm​v6l1 x 11,80053016.05. 01:58
rcs7x86_​642 x 21,80014,39616.05. 05:57
rds0x86_​644 x 21,80031,99216.05. 06:08
r4s7i6864 x 11,83314,66416.05. 03:08
r4s7sx86_​642 x 11,8337,33216.05. 03:09
r1s8sx86_​644 x 11,90015,19616.05. 02:00
res8sx86_​644 x 11,90015,05216.05. 06:40
res8x86_​644 x 11,90015,05216.05. 06:38
res4sx86_​644 x 11,90015,05216.05. 06:29
res4x86_​644 x 11,90015,05216.05. 06:28
rds3x86_​644 x 11,91015,32416.05. 06:13
rds4x86_​644 x 11,91015,32416.05. 06:14
rds2x86_​644 x 11,91015,32416.05. 06:12
rds1x86_​644 x 11,91015,32416.05. 06:10
rbs6x86_​644 x 11,91515,32416.05. 05:29
rfs0x86_​6416 x 22,000128,00016.05. 06:42
res3x86_​644 x 12,00015,97216.05. 06:25
r9s1x86_​642 x 12,0003,99216.05. 04:41
r6s1x86_​642 x 12,0007,97816.05. 03:44
ras3aarch​648 x 12,0004,00016.05. 05:07
ras6aarch​648 x 12,0003,20016.05. 05:11
r5s3x86_​644 x 22,00031,87216.05. 03:18
rbs2x86_​644 x 12,00015,97216.05. 05:19
rbs1x86_​644 x 12,00015,97216.05. 05:18
r8s2x86_​642 x 22,10016,76016.05. 04:23
r8s2sx86_​642 x 22,10016,76016.05. 04:25
r1s6x86_​642 x 22,13017,06416.05. 01:54
r5s0x86_​642 x 22,20017,58216.05. 03:14
res5sx86_​642 x 22,20019,20016.05. 06:32
res5x86_​642 x 22,20019,20016.05. 06:31
r6s3x86_​644 x 22,20035,12016.05. 03:48
r6s8x86_​642 x 22,30018,35616.05. 03:57
r4s0x86_​642 x 22,30018,39615.05. 14:46
r0s1x86_​644 x 22,30055,99216.05. 01:12
r1s2sx86_​644 x 12,30028,00016.05. 01:48
r1s2x86_​644 x 12,30028,00016.05. 01:46
r7s0x86_​642 x 22,30018,40016.05. 03:59
ras0x86_​642 x 22,30018,41616.05. 05:02
r9s0x86_​642 x 22,30018,40016.05. 04:40
r8s0x86_​642 x 22,30018,40016.05. 04:20
r6s7i6862 x 12,3009,17611.01. 02:44
r7s7sx86_​642 x 22,30018,39616.05. 04:15
r3s1i6864 x 12,40019,12716.05. 02:18
rbs8sx86_​644 x 22,40038,70416.05. 05:37
rcs0x86_​648 x 22,40076,60016.05. 05:40
r2s7aarch​644 x 12,40043216.05. 02:10
rbs0i6862 x 22,50017,60016.05. 05:17
r0s0x86_​644 x 22,50040,00016.05. 01:10
r5s4x86_​642 x 22,53020,26416.05. 03:22
r5s4sx86_​642 x 22,53020,26416.05. 03:24
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s1x86_​642 x 22,60021,69616.05. 01:45
r8s3x86_​644 x 12,66721,28016.05. 04:27
r3s6sx86_​642 x 22,66721,33216.05. 02:36
r9s5x86_​642 x 12,70010,77413.07. 03:15
r5s2x86_​644 x 12,70021,69916.05. 03:16
r8s7x86_​642 x 12,70010,77616.05. 04:34
rcs5x86_​642 x 12,80011,19816.05. 05:53
rcs5sx86_​642 x 12,80011,19816.05. 05:55
rcs2x86_​642 x 12,80011,23216.05. 05:44
r1s3x86_​644 x 12,80022,42416.05. 01:50
r9s6x86_​642 x 23,00023,94416.05. 04:57
r9s3sx86_​644 x 13,00024,00016.05. 04:45
r2s0x86_​644 x 13,10024,80016.05. 02:01
r1s0x86_​644 x 13,10024,79616.05. 01:43
r3s8i6866 x 13,20038,52616.05. 02:38
rcs3sx86_​644 x 23,30052,69616.05. 05:47
r8s7sx86_​642 x 13,30013,19816.05. 04:36
r0s1sx86_​644 x 23,30052,67216.05. 01:13
rcs8sx86_​644 x 23,30052,79216.05. 06:07
r3s3x86_​646 x 23,33379,99216.05. 02:23
r5s1x86_​646 x 13,33340,09216.05. 03:15
r4s6x86_​644 x 23,40054,25616.05. 03:01
r8s5i6864 x 23,40054,40016.05. 04:32
rcs1x86_​646 x 23,46783,37616.05. 05:42
r0s8sx86_​646 x 23,47083,38816.05. 01:41
rcs6x86_​644 x 23,50063,99211.05. 17:51
rbs2sx86_​641 x 13,500007.09. 15:06
r9s5sx86_​642 x 13,50013,99816.05. 04:55
r0s2x86_​644 x 23,50055,86416.05. 01:15
r0s5x86_​648 x 23,500115,20015.05. 13:30
r3s0i6864 x 23,50055,99216.05. 02:16
r0s3sx86_​644 x 23,60067,20016.05. 01:21
r0s6x86_​648 x 23,600115,20016.05. 01:27
r0s4sx86_​648 x 23,600115,20016.05. 01:25
r0s5sx86_​648 x 23,600115,20015.05. 01:28
r0s4x86_​648 x 23,600115,20016.05. 01:24
r0s7x86_​648 x 23,600115,20016.05. 01:33
r0s8x86_​648 x 23,600115,20016.05. 01:39
r0s3x86_​648 x 23,600115,20016.05. 01:17
r0s6sx86_​6410 x 23,700147,98016.05. 01:30
r0s2sx86_​6410 x 13,70073,99015.05. 13:17
r0s7sx86_​642 x 23,70029,52816.05. 01:37
rcs8x86_​6416 x 23,700217,15216.05. 06:05
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

Valid XHTML 1.0 Transitional