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2024-05-08 - 17:35

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (by cores) - (x86 CPU strings)

BoxArchCoresMHz ↑Bogo​MIPSEffective
rbs5i6864 x 2049,53908.05. 16:48
r9s1sarm​v7l1 x 101,25014.04. 18:03
r3s2sriscv644 x 1028408.05. 14:13
res6saarch​644 x 101,60008.05. 05:50
r3s5i5861 x 113326508.05. 14:21
r2s1arm​v5tejl1 x 120019908.05. 13:59
r8s1i5861 x 135070108.05. 15:44
r2s5ppc1 x 13966627.03. 13:43
ras7ppc1 x 13966508.05. 16:35
r1s4sarm​v7l2 x 14004808.05. 13:50
r4s8arm​v7l1 x 140039808.05. 14:55
r2s8ppc1 x 14006608.05. 14:08
r4s8sarm​v7l1 x 140039808.05. 14:56
r8s6arm​v7l1 x 150049808.05. 15:55
r4s5arm​v7l1 x 1500008.05. 14:47
r4s3i5861 x 150099608.05. 14:41
ras4arm​v7l1 x 150039808.05. 16:28
r5s7sarm​v7l1 x 15286408.05. 15:13
r5s7arm​v7l1 x 15284808.05. 15:11
r3s7i6861 x 15331,06608.05. 14:27
r5s6ppc1 x 153313308.05. 15:10
r7s4arm​v7l1 x 153634808.05. 15:34
r5s5sarm​v7l1 x 160060001.05. 15:04
r2s3sarm​v7l0 x 1 x 16001,20008.05. 14:01
r5s5arm​v7l1 x 160059708.05. 15:08
ras4sarm​v7l1 x 160059707.02. 02:45
r2s3arm​v7l0 x 1 x 162462408.05. 14:00
rbs8arm​v7l2 x 16662,65008.05. 16:59
r7s3arm​v6l1 x 1700508.05. 15:28
r2s2arm​v7l1 x 172049908.05. 14:00
rfs4arm​v7l1 x 180080008.05. 05:58
r9s8sarm​v7l1 x 180079608.05. 16:21
r4s2sarm​v7l1 x 180053008.05. 14:37
r4s2arm​v7l1 x 180079608.05. 14:35
rfs4sarm​v7l1 x 180080008.05. 06:04
r2s4mips​641 x 180053124.12. 13:46
rbs7arm​v7l4 x 19961208.05. 16:55
rbs3arm​v7l4 x 19962408.05. 16:42
rbs7sarm​v7l4 x 19962408.05. 16:56
r9s4i6861 x 21,0003,99008.05. 16:10
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
r3s2riscv641 x 11,00028408.05. 14:12
r4s6sarm​v7l0 x 1 x 11,0006608.05. 14:51
ras6sarm​v7l1 x 11,0001,98708.05. 16:34
r7s8arm​v7l1 x 11,00099508.05. 15:40
ras5arm​v7l2 x 11,0002408.05. 16:29
res3saarch​640 x 1 x 11,0001,60008.05. 05:43
r7s6arm​v7l1 x 11,00039828.02. 14:10
ras5sarm​v7l2 x 11,0002408.05. 16:31
res7arm​v7l0 x 1 x 11,0001208.05. 05:52
r7s8sarm​v7l1 x 11,00079608.05. 15:42
r9s7arm​v7l2 x 11,000008.05. 16:21
ras2x86_​642 x 11,0674,26608.05. 16:25
rcs4x86_​642 x 11,1004,37608.05. 17:12
r6s4x86_​642 x 11,1004,37608.05. 15:20
rcs4sx86_​644 x 11,1008,75208.05. 17:14
res6x86_​644 x 11,1008,75208.05. 05:49
r4s4ppc4 x 11,20049808.05. 14:43
r1s5aarch​644 x 11,20079608.05. 13:51
r3s5sppc2 x 11,20040008.05. 14:23
r1s4arm​v7l2 x 11,2004808.05. 13:49
rbs4x86_​644 x 11,2009,60008.05. 16:46
ras3sarm​v7l1 x 11,30084008.05. 16:27
r3s4aarch​646 x 11,3009608.05. 14:16
r7s5i6861 x 11,3002,59308.05. 15:36
r8s8x86_​642 x 11,3005,14408.05. 16:00
rbs6sx86_​642 x 11,3335,33208.05. 16:53
r9s4sx86_​642 x 11,3335,34708.05. 16:16
r2s6saarch​644 x 11,3506408.05. 14:04
rcs3i6862 x 11,4005,58608.05. 17:08
rbs3sarm​v7l4 x 11,40035608.05. 16:43
r7s3sarm​v7l4 x 11,40035608.05. 15:31
ras1i6861 x 11,4002,79908.05. 16:25
r4s3si6861 x 11,4662,93208.05. 14:42
r2s7saarch​644 x 11,50043208.05. 14:07
rfs1aarch​644 x 11,50043208.05. 05:57
rfs2aarch​644 x 11,50043208.05. 05:57
r7s2sarm​v7l4 x 11,50072013.07. 02:16
rcs7sx86_​644 x 11,50011,98008.05. 17:20
r2s6i6861 x 11,5002,99908.05. 14:03
r6s5i6861 x 11,5001,12208.05. 15:21
r7s4sarm​v7l4 x 11,5001,08008.05. 15:35
r4s1sarm​v7l4 x 11,5001,08008.05. 14:33
r4s1arm​v7l4 x 11,5001,08008.05. 14:31
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r8s4sx86_​644 x 21,60028,80008.05. 15:52
r7s7x86_​644 x 11,60012,76708.05. 15:37
res1sx86_​644 x 11,60014,40008.05. 05:40
rds7x86_​644 x 11,60012,74808.05. 05:36
rds5x86_​644 x 11,60012,74808.05. 05:33
ras8x86_​644 x 11,60014,40008.05. 16:35
r9s3x86_​644 x 11,60012,74808.05. 16:07
r9s2x86_​644 x 11,60012,74808.05. 16:05
rds6x86_​644 x 11,60012,74808.05. 17:35
ras8sx86_​644 x 11,60012,74808.05. 16:37
rbs4sx86_​644 x 11,60012,74808.05. 16:47
res2x86_​644 x 11,60014,40008.05. 05:40
r6s6i6861 x 11,6003,19108.05. 15:24
res1x86_​644 x 11,60014,40008.05. 05:39
rds8x86_​644 x 11,60012,74808.05. 05:36
r4s5saarch​644 x 11,60020027.03. 14:13
r5s3sx86_​644 x 11,60012,74808.05. 15:01
r7s1x86_​644 x 11,60012,84008.05. 15:27
r8s4x86_​644 x 21,60028,80008.05. 15:50
rbs5saarch​644 x 11,6006408.05. 16:50
r1s8i6861 x 21,6006,39808.05. 13:55
r3s6x86_​641 x 11,6603,33308.05. 14:24
r1s6sx86_​642 x 21,66713,33208.05. 13:53
r6s2x86_​642 x 11,6679,57808.05. 15:17
r6s0x86_​642 x 10 x 21,700136,18008.05. 15:15
res0x86_​644 x 21,80031,99208.05. 05:37
r1s7arm​v6l1 x 11,80053008.05. 13:55
rcs7x86_​642 x 21,80014,39608.05. 17:19
rds0x86_​644 x 21,80031,99208.05. 17:28
r4s7i6864 x 11,83314,66408.05. 14:52
r4s7sx86_​642 x 11,8337,33208.05. 14:54
r1s8sx86_​644 x 11,90015,19608.05. 13:57
res8sx86_​644 x 11,90015,05208.05. 05:55
res8x86_​644 x 11,90015,05208.05. 05:53
res4sx86_​644 x 11,90015,05208.05. 05:45
res4x86_​644 x 11,90015,05208.05. 05:44
rds3x86_​644 x 11,91015,32408.05. 17:32
rds4x86_​644 x 11,91015,32408.05. 17:33
rds2x86_​644 x 11,91015,32408.05. 17:31
rds1x86_​644 x 11,91015,32408.05. 17:29
rbs6x86_​644 x 11,91515,32408.05. 04:44
rfs0x86_​6416 x 22,000128,00008.05. 05:56
res3x86_​644 x 12,00015,97208.05. 05:42
r9s1x86_​642 x 12,0003,99208.05. 16:03
r6s1x86_​642 x 12,0007,97808.05. 15:16
ras3aarch​648 x 12,0004,00008.05. 16:27
ras6aarch​648 x 12,0003,20008.05. 16:32
r5s3x86_​644 x 22,00031,87208.05. 15:00
rbs2x86_​644 x 12,00015,97208.05. 16:41
rbs1x86_​644 x 12,00015,97208.05. 16:40
r8s2x86_​642 x 22,10016,76008.05. 15:45
r8s2sx86_​642 x 22,10016,76008.05. 15:47
r1s6x86_​642 x 22,13017,06408.05. 13:52
r5s0x86_​642 x 22,20017,58208.05. 14:57
res5sx86_​642 x 22,20019,20008.05. 05:48
res5x86_​642 x 22,20019,20008.05. 05:46
r6s3x86_​644 x 22,20035,12008.05. 15:18
r6s8x86_​642 x 22,30018,35608.05. 15:25
r4s0x86_​642 x 22,30018,39608.05. 14:29
r0s1x86_​644 x 22,30055,99208.05. 13:11
r1s2sx86_​644 x 12,30028,00008.05. 13:46
r1s2x86_​644 x 12,30028,00008.05. 13:45
r7s0x86_​642 x 22,30018,40008.05. 15:26
ras0x86_​642 x 22,30018,41608.05. 16:23
r9s0x86_​642 x 22,30018,40008.05. 16:01
r8s0x86_​642 x 22,30018,40008.05. 15:42
r6s7i6862 x 12,3009,17611.01. 02:44
r7s7sx86_​642 x 22,30018,39608.05. 15:39
r3s1i6864 x 12,40019,12708.05. 14:11
rbs8sx86_​644 x 22,40038,70408.05. 17:00
rcs0x86_​648 x 22,40076,60008.05. 17:04
r2s7aarch​644 x 12,40043208.05. 14:05
rbs0i6862 x 22,50017,60008.05. 16:39
r0s0x86_​644 x 22,50040,00008.05. 13:10
r5s4x86_​642 x 22,53020,26408.05. 15:03
r5s4sx86_​642 x 22,53020,26408.05. 15:05
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s1x86_​642 x 22,60021,69608.05. 13:43
r8s3x86_​644 x 12,66721,28008.05. 15:49
r3s6sx86_​642 x 22,66721,33208.05. 14:25
r9s5x86_​642 x 12,70010,77413.07. 03:15
r5s2x86_​644 x 12,70021,69908.05. 14:59
r8s7x86_​642 x 12,70010,77608.05. 15:56
rcs5x86_​642 x 12,80011,19808.05. 17:15
rcs5sx86_​642 x 12,80011,19808.05. 17:17
rcs2x86_​642 x 12,80011,23208.05. 17:07
r1s3x86_​644 x 12,80022,42408.05. 13:48
r9s6x86_​642 x 23,00023,94408.05. 16:19
r9s3sx86_​644 x 13,00024,00008.05. 16:08
r2s0x86_​644 x 13,10024,80008.05. 13:57
r1s0x86_​644 x 13,10024,79608.05. 13:42
r3s8i6866 x 13,20038,52608.05. 14:28
rcs3sx86_​644 x 23,30052,69608.05. 17:10
r8s7sx86_​642 x 13,30013,19808.05. 15:57
r0s1sx86_​644 x 23,30052,67208.05. 13:12
rcs8sx86_​644 x 23,30052,79208.05. 17:27
r3s3x86_​646 x 23,33379,99208.05. 14:14
r5s1x86_​646 x 13,33340,09208.05. 14:58
r4s6x86_​644 x 23,40054,25608.05. 14:48
r8s5i6864 x 23,40054,40008.05. 15:53
rcs1x86_​646 x 23,46783,37608.05. 17:06
r0s8sx86_​646 x 23,47083,38808.05. 13:41
rcs6x86_​644 x 23,50063,99208.05. 17:18
rbs2sx86_​641 x 13,500007.09. 15:06
r9s5sx86_​642 x 13,50013,99808.05. 16:17
r0s2x86_​644 x 23,50055,86408.05. 13:13
r0s5x86_​648 x 23,500115,20008.05. 13:25
r3s0i6864 x 23,50055,99208.05. 14:10
r0s3sx86_​644 x 23,60067,20008.05. 13:20
r0s6x86_​648 x 23,600115,20008.05. 13:28
r0s4sx86_​648 x 23,600115,20008.05. 13:23
r0s5sx86_​648 x 23,600115,20008.05. 13:27
r0s4x86_​648 x 23,600115,20008.05. 13:22
r0s7x86_​648 x 23,600115,20008.05. 13:33
r0s8x86_​648 x 23,600115,20008.05. 13:39
r0s3x86_​648 x 23,600115,20008.05. 13:16
r0s6sx86_​6410 x 23,700147,98008.05. 13:30
r0s2sx86_​6410 x 13,70073,99008.05. 13:15
r0s7sx86_​642 x 23,70029,52808.05. 13:37
rcs8x86_​6416 x 23,700217,15208.05. 17:26
r5s2sx86_​644 x 24,00063,86312.04. 01:34
 

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